JTAG Guidelines for Board DFT - Part 2:

Guidelines for Board Design For Test (DFT) Based on Boundary Scan or JTAG

Part 2

Prepared by Ben Bennetts, DFT Consultant for ASSET InterTech, Inc.

April 2006

ABSTRACT:

This document is Part 2 of a 2-part document that contains a series of DFT JTAG Guidelines for boards to be tested primarily through the use of boundary scan, based on the IEEE 1149.1-2001 Standard.

Any comments, corrections, suggested additions should be sent to the author, Ben Bennetts, at ben@dft.co.uk.

In this section, we will look at DFT JTAG guidelines specific to the design of boards containing non-boundary-scan clusters and the special case of RAM and PLD clusters (in-system configuration).

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