JTAG Guidelines for Board DFT - Part 1: 

Be careful with the design and distribution of the on-board TAP signals. Allow direct access to all TAP signals from the primary contact to the board: edge connector or plug and socket. Treat both TCK and TMS as critical signals i.e. properly balanced, no skew, properly buffered (with no inversion), monotonic (continuously rising/falling), etc. Terminate the signals to avoid reflections. Note that the TCK frequency is determined by the slowest device on the board. (Maximum TCK frequency for a device is specified in the BSDL file for that device.) Place a weak pull down on the TRST* signal – see later.

It is recommended to buffer the primary TAP signals on/off the board for the following reasons:

• to prevent noisy backplane signals from reaching the on-board devices;
• to handle impedance mismatches between tester and the board, tester drivers and board fanouts, cable length etc.;
• to allow for a faster speed TCK because impedance mismatch issues can be minimized and possibly matched with the tester through a special buffer board;
• to not limit the cable length between the tester and the board; and
• to allow safe states to be maintained on the signals during normal use and during test use (if the tester-to-board cable becomes disconnected).

Where designs have buffers and you want to change them for scan devices, the usual problem is that scanable buffers on the market tend to be a bit out-of-date and too slow or the wrong voltage/technology. So why not use a programmable logic device? It is relatively easy to design a CPLD or FPGA to act as a buffer of almost any complexity. You may even absorb several buffers into one programmable logic device, saving board space. They are usually more than fast enough, and many not-so-new ones are very cheap now.

Be careful with the design and distribution of the on-board TAP signals. Treat both TCK and TMS as critical signals i.e. properly balanced, no skew, properly buffered (with no inversion), etc. But note that what really counts between TCK and TMS is that TMS is stable when a value change on TCK occurs.

Terminate the signals to avoid reflections. Note that the TCK frequency is determined by the slowest device on the board. (Maximum TCK frequency for an 1149.1 device is specified in the BSDL file for that device.)

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