JTAG Chip DFT: 

As you will appreciate, the BSDL files must be 100% accurate. Any slight error in the data can completely disrupt the board-level pattern generation processes and cause anomalous behavior which can become very difficult to diagnose correctly. It is strongly recommended that BSDL files are checked both syntactically and semantically before they are used by the board-level pattern-generation and pattern-application processes. There are commercial checkers available, from companies such as ASSET InterTech (www.asset-intertech.com).

The final proof of correctness is to compute 1149.1 conformance tests from the apparently correct BSDL, and then apply these tests to a device on either a chip tester or even a PC-based tester. You are strongly urged to carry out both the syntax and semantic tests, and then to generate and apply conformance tests on real silicon before using BSDL files “in anger”.

Bidirectional (IO) and three-state (OZ) pins require status-control boundary-scan or JTAG cells so that their status can be controlled whilst the device is in its test mode. Often the status control is based on an input pin, such as an Output_Enable pin. If the control is internal, extra boundary-scan or JTAG cells are inserted in the boundary-scan (JTAG) register. Such scan cells should control the IO and OZ pins is a way that conforms to the natural use of the IO or OZ pins. This prevents unnatural test configurations at board level that might place other on-board devices into a potentially dangerous state.

TRST* is an optional active-low asynchronous reset signal for the 1149.1 logic. There always exists a synchronous reset, initiated by holding the TMS signal at logic 1 and applying five consecutive TCK clocks (the so-called “TMS = 1, 5 x TCK” cycle) but, as we will see later when we reach the board guidelines section, there are very good reasons to also incorporate the optional TRST* feature. There are also very good reasons to insert a Power-On-Reset (POR) circuit to the TAP controller even if the optional TRST* is inserted. Note: POR is not mandated if the TRST* signal is inserted.

It is ironical that the only way to find pin-to-pin shorts at the board level is by deliberately creating contention on two driver scan cells i.e. causing one driver to drive a logic 1 and the other to drive a logic 0. If the short is present, then we assume that it is either a strong-1 weak-0 (Wired-OR) short or weak-1 strong-0 (Wired-AND) short. Such a test places a stress on the output drivers since one output will dominate, forcing the other to its opposite logic value and possibly damaging the output drive amplifier of the weaker signal. In the world of in-circuit test, this problem is known as node forcing or back driving and steps can be taken to reduce the amount of time the outputs are under stress. In the JTAG or boundary scan world, the time it takes to apply all the interconnect tests is a function of the complete length of the JTAG (boundary-scan) chain, the number of interconnect patterns, and the frequency of TCK. This time may become too long and irreversible damage can occur to one of the output drivers. You will need to determine the vulnerability of the outputs to such damage.

In the example above, the assumption is that the short behaves like a strong 1 weak 0 (Wired-OR) short, and the initial 10 stimulus values in the driver scan cells are received as 11 response values in the sensor scan cells. Once the received values are off-loaded from the board, the presence of the short will be known.

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