JTAG Chip DFT:

CHIP-LEVEL DFT GUIDELINES:

In this document, we will look at DFT guidelines specific to the design of boards to be tested through the boundary-scan/JTAG registers of IEEE 1149.1-compliant devices. Since the 1149.1 structures are incorporated inside the compliant devices, many of the guidelines relate to the specification of optional features inside the devices i.e. are device-level DFT guidelines. Accordingly, the first part of the document considers the device-level guidelines.

First and foremost, we should ask “who drives the specification for JTAG/boundary-scan features inside new ASICs and SoC devices?”. The answer is “all those who will benefit from the use of boundary scan or JTAG” – that is, prototype board debug engineers, board test programmers, system integrators, and field service repair engineers. It’s also worth adding device procurement people to the group. This makes such people conscious of the need to buy 1149.1-compliant devices. Consequently, the correct way to specify the 1149.1 features in a new ASIC or SoC is for all these people to sit down and decide the product life-time strategy for testing the boards. Each engineer will have a different view of the requirements specification and, collectively, the group can try to come up with a consensus view of the overall requirement, but note: obtaining a consensus view can be difficult!!

Once specified, the requirement can be presented to the chip designer in the form of a BSDL file. But note that some 1149.1 chip-level boundary-scan (JTAG) synthesis programs cannot accept BSDL as an input specification. Check with your vendor.

All devices should be 100% compliant with the 1149.1 Standard.

It is a good habit to specify all the optional public instructions (e.g. IDCODE, CLAMP, HIGHZ, etc) by default and only remove them if it can be shown that they will never be used or that they cause violation of another design requirement. IDCODE allows identification of the device manufacturer plus the part number and version number. It also supports a higher-quality board-level scan-chain integrity test.

IC vendors should have checked all 1149.1 features before shipping the parts to system companies. Make sure they have done this. You do not want to find a faulty 1149.1 part once it has been bonded to the board.

Strictly speaking, there should not be any non-compliant 1149.1 devices!! But, if the vendor has done something that does not comply (tying TRST* low inside the device is a common non-compliant feature), make sure the non-compliance is documented. Non-compliance can be documented in the Design Warnings section of a BSDL file.

Last, but not least, validate the BSDL files – next slide.

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