JTAG Chip DFT:

Guidelines for Chip Design For Test (DFT) Based on Boundary Scan or JTAG

Prepared by Ben Bennetts, DFT Consultant for ASSET InterTech, Inc.

April 2006

ABSTRACT:

This document contains DFT Guidelines for devices to be tested primarily through the use of boundary scan (JTAG), based on the IEEE 1149.1-2001 Standard.

Any comments, corrections, suggested additions should be sent to the author, Ben Bennetts, at ben@dft.co.uk.

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