Boundary-Scan Tutorial:

Summary

To summarize, the basic motivation for boundary scan was the miniaturization of device packaging, the development of surface-mounted packaging, and the associated development of the multi-layer board to accommodate the extra interconnects between the increased density of devices on the board. These factors led to a reduction of the one thing an in-circuit tester requires: physical access for the bed-of-nails probes.

The long-term solution to this reduction in physical probe access was to consider building the access inside the device i.e. a boundary scan register. In the next section, we will take a look at the device-level architecture of a boundary-scan device, and begin to understand how the boundary-scan register solves the limited-access board-test problem.

In a boundary-scan device, each digital primary input signal and primary output signal is supplemented with a multi-purpose memory element called a boundary-scan cell. Cells on device primary inputs are referred to as “ input cells ”; cells on primary outputs are referred to as “ output cells .” “ Input ” and “ output ” is relative to the internal logic of the device. (Later, we will see that it is more convenient to reference the terms “ input ” and “ output ” to the interconnect between two or more devices.) See Figure 10.

The collection of boundary-scan cells is configured into a parallel-in, parallel-out shift register. A parallel load operation — called a Capture operation — causes signal values on device input pins to be loaded into input cells, and signal values passing from the internal logic to device output pins to be loaded into output cells. A parallel unload operation — called an Update operation — causes signal values already present in the output scan cells to be passed out through the device output pins. Signal values already present in the input scan cells will be passed into the internal logic.

Data can also be Shifted around the shift register, in serial mode, starting from a dedicated device input pin called Test Data In (TDI ) and terminating at a dedicated device output pin called Test Data Out (TDO) . The Test ClocK , TCK , is fed in via yet another dedicated device input pin and the various modes of operation are controlled by a dedicated Test Mode Select (TMS ) serial control signal.

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