Boundary-Scan Tutorial:

The Motivation for Boundary-Scan Architecture
Historical Development: In-Circuit Test

Since the mid-1970s, the structural testing of loaded printed circuit boards has relied very heavily on the use of the so-called in-circuit bed-of-nails technique (see Figure 5). This method of testing makes use of a fixture containing a bed-of-nails to access individual devices on the board through test lands laid into the copper interconnect, or into other convenient physical contact points. Testing then proceeds in two phases: power-off tests followed by power-on tests. Power-off tests check the integrity of the physical contact between nail and the on-board access point, followed by open and shorts tests based on impedance measurements.

Power-on tests apply stimulus to a chosen device, or collection of devices (known as a cluster), with an accompanying measurement of the response from that device or cluster. Other devices that are electrically connected to the device-under-test are usually placed into a safe state (a process called “guarding”). In this way, the tester is able to check the presence, orientation, and bonding of the device-under-test in place on the board.

Changes in Device Packaging Styles

Fundamentally, the in-circuit bed-of-nails technique relied on physical access to all devices on a board. For plated-through-hole technology, the access is usually gained by adding test lands into the interconnects on the “B” side of the board — that is, the solder side of the board. The advent of onserted devices packaged in surface mount styles – see Figure 6 - meant that system manufacturers began to place components on both sides of the board — the “A” side and the “B” side. The smaller pitch between the leads of surface-mount components caused a corresponding decrease in the physical distance between the interconnects.

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