Boundary-Scan Tutorial:

For further, more recent publications on boundary-scan topics, see the To Probe Further section at the end of this tutorial.

Course Pre-Requisites

Students who participate in this course are expected to know the basics of logic design plus have a general understanding of Integrated Circuit design principles and Printed-Circuit Board electronic design, board assembly and test techniques.

Dr R G “Ben” Bennetts is an independent consultant in Design-For-Test (DFT), consulting in product life-cycle DFT strategies, and delivering on-site and open educational courses in DFT technologies. Previously, he has worked for LogicVision, Synopsys, GenRad and Cirrus Computers. Between 1986 and 1993, he was a free-lance consultant and lecturer on Design-for-Test (DFT) topics. During this time, he was a member of JTAG, the organization that created the IEEE 1149.1 Boundary-Scan Standard. He is an Advisory member of the Board of Directors of ASSET InterTech.

Ben has published over 90 papers plus three books on test and DFT subjects.

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