Tackling tough problems
By Reg Waller, ASSET InterTech, Inc.
Embedded System Engineering, (Sept. 2005)

Boundary scan (JTAG) can provide testing throughout the product life cycle, even in hard to reach places.

Faults and failures in embedded systems are quite different from failures in other types of electronic systems. Many embedded systems are in hard-to-reach places. They could be tucked away in the corner of a manufacturing plant in a factory automation system or in a wireless base station in the middle of a desert. Servicing an embedded system is often difficult and usually expensive. In addition, embedded applications are sometimes high-availability systems, whose providers have guaranteed a certain level of service and can be penalized monetarily when the system does not perform as specified.

With this kind of situation, it's no small wonder that embedded system designers are interested in IEEE 1149.1 boundary scan, often known as JTAG after the Joint Test Action Group which provided the impetus for the standard. Boundary scan is a technology that increases test coverage and ensures higher quality systems by identifying and isolating structural faults during every stage of a system's life cycle. Circuit boards are becoming so dense that test pads are disappearing and access to device pins is becoming scarcer with the proliferation of lead-less chip scale packages, boundary scan can increase test coverage without requiring physical access to test pads or device pins.

Better test coverage with boundary scan can quickly ferret out those unseen structural faults or failures during design debug and validation, during assembly and manufacturing, and even later after the system has been installed. As a result, higher quality systems are shipped to the field and, when troubleshooting is needed, the cause of a structural failure is identified faster, returning the system to service in short order.

Figure 1: Embedded Boundary Scan

Another important use of boundary scan is in-system programming. The four-wire JTAG infrastructure on a circuit board is available to reconfigure programmable logic devices (PLDs) or load data into memory. System-level JTAG techniques can enable remote access via the Internet, for example, to PLDs or memories. For embedded systems in far-away or hard-to-reach places, downloading firmware upgrades remotely without dispatching a technician can reduce costs tremendously. (Figure 1)

What is boundary scan?
Boundary scan is designed into chips, circuit boards and systems. Boundary scan chips have a multi-purpose memory element called a boundary-scan cell. A circuit board's collection of boundary-scan cells is configured into a parallel­in, parallel-out shift register by way of the four­wire JTAG interface. Data can be shifted into and out of the scan chain that connects the boundary scan cells on multiple devices on one or more circuit boards or assemblies in the system. This device-level access can also be used to load data into PLDs or memories.

Devices that do not have embedded boundary-scan cells can still be tested by boundary scan. A boundary-scan device directly connected to a non-boundary-scan device can drive signals onto the non-boundary-scan device and test its interconnects in this way.

How is boundary scan used?
Boundary scan can be used to test the interconnection between a chip and a circuit board as well as the structural integrity of assembled circuit boards. And if the board-level boundary-scan facilities are connected and a system-level JTAG architecture established, then system-level boundary-scan operations can also be conducted.

For embedded systems, many of which are subjected to harsh environmental conditions, system-level JTAG operations can be very beneficial. For example, many companies use techniques such as HALT (Highly Accelerated Life Testing) or other environmental tests as part of the design validation process. If a manufacturing fault is detected, system-level JTAG diagnostics can identify net- or pin-level faults and eliminate the time the test group might spend trying to find a design fault. System-level boundary scan is available in the environmental test chamber at whatever temperature or at whatever level of stress the system is subjected to.

Fast ROI
Boundary scan's return-on-investment (ROI) is very fast since it can reduce costs during every phase of an embedded system's life. Beginning with the design phase, boundary scan can help developers quickly validate a design or debug a problematic prototype circuit board.

As part of the assembly and manufacturing process, the increased test coverage made possible by the embedded JTAG infrastructure will yield higher quality systems, which leads to increased reliability and durability. In addition, problems on any failed circuit boards or assemblies can be rapidly diagnosed down to the level of a particular pin on a device. With this kind of information, repair operations are much more effective and the firm's investment in assembled but failed circuit boards can be recouped.

Lastly, after embedded systems are installed, boundary scan can reduce support costs significantly. For example, many providers of embedded systems must contend with the "no fault found" (NFF) condition. To return a high-availability system to service quickly, technicians routinely remove and replace one or more circuit boards that might be the cause the problem. Subsequently, the questionable boards are test­ed and a high percentage of them are often classified as "no-fault-found." NFF boards are some­times returned to service where the costly cycle of failure, troubleshooting and testing begins again. The precise diagnostic capabilities of system-level JTAG can eliminate the guesswork and drastically reduce the NFF costs.

Ultimately, developers of embedded systems are finding that designing boundary scan into their applications has a big payoff in terms of reducing the cost of test and support, improving the quality and reliability of their products, and simplifying the way software updates are loaded into systems in the field.