Boundary
scan's horizons are expanding
By Reg Waller, ASSET InterTech, Inc.
Components
in Electronics, (June 2005) p. 12
Since its introduction, the boundary scan infrastructure
has proved itself versatile and highly adaptable. Reg Waller,
European sales director at ASSET InterTech, explains why
the technology is increasingly being used at the system test
level.
When the boundary-scan standard (IEEE 1149.1) was conceived
by the Joint Test Action Group (JTAG), the technology was
thought of as a simple, low-cost way of testing dense circuit
boards where physical access to device pins and test pads
was quickly disappearing. Over the years, boundary scan,
or simply JTAG, as it is sometimes referred to, has evolved
into much more.
Boundary scan has become an invaluable embedded communication
technology, serving applications that had not yet been envisioned
when it was being developed. Over the years since its definition,
JTAG has spawned an entire class of test and programming
methods and techniques. These include: IEEE 1532 in-system
configuration (18C) of programmable logic devices, in-system
programming (18P) of flash memory, the IEEE 1149.4 analogue
test standard, emulation techniques as well as processor-based
emulation testing, the IEEE 1149.6 standard for testing of
high-speed ac-coupled buses, and the proprietary embedded
method, Intel IBIST (Interconnect Built-In Self Test).
Using the boundary-scan infrastructure
For boundary scan to take on the role of a board- and system-level infrastructure
for other test and programming techniques, the boundary-scan test system,
which is used to develop and apply JTAG tests, must be easy to use yet powerful
in the functionality it offers. With such a system, a firm's design, manufacturing
or support group is capable of not only checking for shorts and opens - the
first applications for boundary scan interconnect tests - but can also perform
a host of other test and in-system programming functions. Combining powerful
and easy to use tools in a boundary scan system will drive down development
and manufacturing costs by increasing efficiency.
For example, both the IEEE 1149.6 Standard for Advanced
Digital Networks and Intel's IBIST methodology are relatively
new techniques for testing and validating the design of high-speed
(10Gb/s) serial buses like Gigabit Ethernet, PCI Express,
Fibre Channel and others with ac-coupled LVDS signalling.
Both IEEE 1149.6 and Intel IBIST make use of and are dependent
upon a system's boundary scan infrastructure. Even the most
ardent supporters of boundary scan could not have foreseen
this eventuality more than a decade ago when boundary scan
was being defined.
The IEEE 1149.6 standard specifies a method for applying
a system's boundary scan capabilities to test a wide variety
of high speed interconnect buses with differential signalling
such as Gigabit Ethernet and Fibre Channel (Figure 1). As
a result, a boundary scan system that supports the new 1149.6
standard can perform both its traditional test functions
on the dc-coupled buses in a design in addition to the 1149.6
tests. 1149.6 tests the high-speed ac-coupled buses that
are becoming increasingly prevalent in certain types of computing
and communication systems. Indeed, many types of systems
such as high speed routers and wireless basestations already
feature hundreds, if not thousands, of these high speed serial
links.
Intel IBIST is a next-generation test method that is being
embedded into that company's chips and chipsets. The onchip
test functionality of Intel IBIST technology depends upon
boundary scan for chip-to-chip communications. The boundary-scan
infrastructure is integral to IBIST's ability to cost effectively
validate the design of high-speed bus structures such as
PCI Express.
Processor-based emulation testing
Another technology that makes use of the boundary scan infrastructure to improve
test coverage is processor-based emulation test. For many years the boundary
scan interface on most microprocessors has been used by software emulators
that run on microprocessors and perform functional tests on the system.
Now, test coverage can be extended by combining traditional
boundary scan testing with processor-based functional emulation
testing on the same boundary scan test system (Figure 2).
When this is done, boundary scan tests can be executed on
complex logic devices such as Ethernet controllers, for example,
that may not have embedded boundary scan capabilities but
which can be accessed by the system's microprocessor. The
two technologies, boundary scan and processor-based functional
emulation testing, extend test coverage well beyond what
either one could provide on its own.
Boundary-scan system test
The benefits of boundary scan are not limited to board level testing and in-system
programming operations. An increasing number of equipment manufacturers are
realizing that testing each component part of a system individually such
as the circuit boards that make up the system does not ensure a fully functional
system when the boards are configured as a system.
For example, a connector could be faulty or a board might
be missing or out of place on the backplane. Functional tests
identify that the system is not functioning as expected,
but isolating and diagnosing the problem with functional
tests is time consuming, expensive and often based on trial
and error. In contrast, the diagnostic and fault-isolation
capabilities of boundary scan are invaluable tools for testing,
locating points of failure and troubleshooting certain structural
aspects of the system as a whole.
Besides system level debug and production test, boundary
scan provides many other system benefits when it is extended
to field support. For example, boundary scan can be used
for quick and easy updates of programs stored in flash memory
or updates to the system's functionality by reconfiguring
on-board PLDs after the system has been installed.
Boundary scan at the system level can be applied in a number
of ways, but the most prevalent method is to design-in one
or more multi-drop boundary-scan gateway devices which control
access to the multiple boundary-scan paths located on individual
boards, backplanes and subassemblies in the system. The gateway
devices can be controlled by an external boundary-scan test
system that connects to the gateway device's boundary-scan
test access port (TAP).
In the future, leading boundary scan vendors will continue
to improve their systems to take full advantage of this technology.
Already, great strides have been made by boundary scan vendors
in terms of automatically generating test patterns and programming
algorithms while ensuring the safety of the board or system
from inadvertent electrical loads. In addition, highly graphical
user interfaces and step-by-step assistance for new or occasional
users has improved the ease of use of some boundary scan
systems dramatically. Boundary scan's role in the electronics
industry will only increase as more applications emerge and
as the power, cost effectiveness and ease of use of boundary-scan
systems continue to advance.
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