ASSET InterTech's Boundary-Scan Test, Processor-Controlled Test and Intel® IBIST form a unique set of tools for access to, and control of embedded instrumentation.
November 3, 2009 - ASSET® InterTech (www.asset-intertech.com), the leading supplier of open tools for embedded instrumentation, and SiliconAid Solutions (www.siliconaid.com), Austin, TX., have formed a strategic relationship whereby ASSET will integrate its first integrated circuit (IC) test tool into the ScanWorks® platform for embedded instrumentation and resell SiliconAid's insertion and verification tools that support the emerging IEEE P1687 Internal JTAG (IJTAG) standard. SiliconAid is a supplier of world class chip verification and debug tools that support the IEEE 1149.1 Boundary-Scan Standard, which is commonly referred to as JTAG after the Joint Test Action Group which initiated development of the standard. Read more »
ASSET’s Al Crouch discusses innovative test strategies for 3D stacked die chips. 3Dincites.com, December 2009
Best in Test Finalists 2010: DFT, boundary scan, and emulation, Test & Measurement World, December 2009
ASSET's ScanWorks Supports PLX Technology's PCI Express Switch Family's visionPAK Diagnostic Toolset, PCBCafe, November 2009
Strategic Relationship with SiliconAid Extends ASSET's ScanWorks Platform Into Chip Test and Verification, Evaluation Engineering, November 2009
ASSET InterTech's Dehne - Seeking Growth in Embedded Instrumentation, Test & Measurement World, July 2009
"Approaching Board Test Non-intrusively" by Alan Sguigna. Evaluation Engineering Magazine, December 2009.
"Embedded Instruments - Messtechnik im Chip" by Al Crouch, elektronik industrie, November 2009.
"Non-Intrusive Board Test Gains Momentum" by Reg Waller, EPN , November 2009.
"Test Standards Emerge to Improve 3D-Chip Yield" by Al Crouch, SOC Central, October 2009.
"Open Tools and Standard Emerge for Embedded Instrumentation" by Al Crouch, Evaluation Engineering, February 2009.
Global recovery, Moore's law, chip packaging and test
New IJTAG standard will generate millions for chip and system manufacturers
“Defect
Coverage for Non-Intrusive Board Tests”
By Adam Ley, chief technologist – boundary scan test
November 2009
“Synergy
of Two Emerging Standards Will Drive 3D Chip and Circuit Board Test into
High Gear”
By Al Crouch, chief technologist – core instrumentation
November 2009
"Economics,
Technology Drive Industry To Non-Intrusive Board Test" -
Alan Sguigna, Vice President, Sales and Marketing
July 2009
DesignCon
Santa Clara, CA
February 2-3, 2010
Embedded
World
Nurnberg, Germnary
March 2-4, 2010
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