PRESS ROOM - PRESS RELEASES

RICHARDSON, TX (February 24, 2004) — The time it takes first-time and occasional users to develop a functional JTAG test, or "time-to-test," has been reduced significantly by the new ScanWorks Assistant from ASSET InterTech. In addition, the latest version of ScanWorks has several other new automation features, including Scan Path Discovery, which streamlines boundary scan test generation, and Multiple Scan Path Support, which provides flexible access to boards with more than one scan path.

ASSET InterTech is an international leader in boundary-scan test and device programming systems. Its ScanWorks environment is currently used by leading electronics companies such as Cisco, Lucent Technologies, Agilent, BAE, Ericsson, Intel, Raytheon, Solectron, Rockwell Collins, EMC and others.

"Our goal is to make the development and application of boundary scan operations an order of magnitude easier," said Dave Bonnett, technical product manager for ASSET. "This is the first in a series of ScanWorks Assistants and this one is specifically targeted at helping with the development of interconnect tests. With Assistant, the engineer or technician doesn't have to be an expert in JTAG to get the most out of boundary scan technology. And that crucial time that it takes to develop the first test and see that it really does work — that's been shortened dramatically."

ScanWorks Assistant

One of the key features of ScanWorks Assistant is the step-by-step advice it offers to new and occasional users. ScanWorks Assistant explains all of the options the user has available and anticipates many of the questions new users typically have about JTAG testing. ScanWorks Assistant shares helpful information, such as how to describe the board being tested, how to generate basic scan path verification and interconnect tests, and how to create a test sequence made up of the test actions to be performed on a particular circuit board or assembly. Beginning with the initial configuration of ScanWorks, informative dialog boxes are automatically activated and displayed during each step of the test development and execution process.

ScanWorks Assistant's dialog boxes feature links to additional information in the event the user requires additional help. While guiding the user through JTAG interconnect test generation step-by-step, ScanWorks Assistant is also teaching the engineer the methodology of boundary scan test. Once the test engineer becomes more familiar with the overall methodologies of the ScanWorks system, ScanWorks Assistant can be turned off so the engineer has direct access to all of the powerful features of ScanWorks.

Scan Path Discovery

Another major feature of ScanWorks is Scan Path Discovery, which uses ScanWorks® TopCAT (Topology and Cluster Analysis Technology) to automatically describe the JTAG scan path on a printed circuit board. Boundary scan systems require a full description of the scan path before any JTAG test or programming operation can be executed. Large, complex or dense boards make this a difficult and time consuming task. Schematics have become quite lengthy, often running to more than 100 pages. Describing a scan path from a schematic can be a tedious process of manually following signals and writing down the integrated circuits along the scan path.

Now though, ScanWorks' Scan Path Discovery automatically finds the devices on a scan path by analyzing a design's netlist and identifying all devices connected to boundary scan signals. Scan Path Discovery then locates the descriptive files for each device on the scan path and constructs a full description of the path. If a device's model is not available or something unexpected is encountered, Scan Path Discovery notifies the user and asks that the needed information be provided.

The user seldom if ever has to consult a hardcopy of a schematic because Scan Path Discovery has a direct link to ScanWorks' Design Browser which provides graphical views of the design and design data. As a final step in the scan path description process, Scan Path Discovery constructs a complete block diagram of the scan path and generates a scan path verification action for ScanWorks to execute.

Multiple Scan Path Support

Another new capability, Multiple Scan Path Support, adds to the flexibility of ScanWorks by simplifying the testing of printed circuit boards with more than one JTAG scan path. Although many designs feature only one scan path because this is the most efficient way to access boundary scan devices, some designs require multiple scan paths. For example, the CPU or complex programmable logic devices on a board may require that they be segregated on their own scan path in order to use certain emulation or programming tools.

With Multiple Scan Path Support, a ScanWorks test action can activate any combination of scan paths on the board. The configuration of the active scan paths may depend on the type of action being executed. For example, the programming of a flash memory device will be accomplished faster when as few devices as possible are on the scan path. In this case, the path could be configured with only a single device on it such as a processor, which would load data into the flash memory device. In contrast, an interconnect test will produce better test coverage if as many devices as possible are configured on the scan path. With Multiple Scan Path Support, ScanWorks can automatically re-configure a printed circuit board's scan path to meet the requirements of a particular test action.

Pricing and Availability

ScanWorks 3.4 with Assistant, Scan Path Discovery and Multiple Scan Path Support will be available from ASSET's direct sales force and its global network of resellers early in the second quarter of 2004. Limited-term licensing for an Interconnect Development Station begins at $6,000. Standard and network licenses are also available, ensuring flexible pricing options and low cost of ownership.

About ASSET InterTech

ASSET InterTech, Inc. develops, markets, sells, and supports boundary-scan testability and in-system programming (ISP) products worldwide. ASSET's PC- and PXI-based ScanWorks' environment allows users to quickly and easily test semiconductors, circuit boards or entire systems during every phase of a product's life, including design, manufacturing/repair and field maintenance. The ISP capabilities of ScanWorks can be used to load software or data into programmable devices after they have already been connected to a printed circuit board. The ScanWorks product family works in conjunction with a standard of the International Electronics and Electrical Engineering (IEEE) society known as the IEEE 1149.1 (JTAG) boundary-scan test specification. ASSET's Ensure DFT' Services provides high-level design-for-test engineering and development services to the electronics industry. ASSET InterTech is located outside of Dallas at 2201 North Central Expressway, Suite 105, Richardson, TX 75080.

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ASSET and ScanWorks are registered trademarks and the ASSET logo and Ensure DFT are trademarks of ASSET InterTech, Inc. All other trade and service marks are the properties of their respective owners.