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ASSET brings JTAG test tools perspective to IEEE 1149.7 Expert in embedded instrumentation participates in development of test access port with reduced pin count and enhanced functionality

Richardson, TX (September 11, 2008) - ASSET® InterTech (www.asset-intertech.com), the leading supplier of open tools for embedded instrumentation, has assumed a principal role in the development of IEEE 1149.7 as one of the founding members of the working group that is defining the emerging standard, which will be ratified in early 2009.

Deriving from an established standard, the IEEE 1149.1 Test Access Port (TAP) and Boundary-scan Architecture, but offering options for a smaller, two-wire interface and enhanced functionality, IEEE 1149.7 extends the test and debug capabilities of IEEE 1149.1 standard's TAP to complex devices like system-on-chip (SOC), system-in-package (SIP), and other multi-core or multi-die devices. In its reduced pin count form factors, IEEE 1149.7 has been targeted for mobile products, but it offers enhanced test functionality for any electronic system.

"Advanced semiconductor devices today are packing the capabilities of entire systems into one device. In fact, SOC and SIP technologies are becoming more and more prevalent," said Adam Ley, ASSET's chief technologist and designated representative to the IEEE 1149.7 working group. "The complexity of these devices requires the embedding of instrumentation to test and debug them, as well as the higher level circuit assemblies in which they are deployed. By participating in the development of IEEE 1149.7, we intend to simplify the access, automation and analysis of embedded instrumentation through the standard test access port, just as we have done for the IEEE 1149.1 boundary-scan standard, and as we are doing for another emerging embedded instrumentation standard, IEEE P1687 (also known as Internal JTAG or IJTAG). In fact, we view all of these standards as complementary and synergistic."

"Once the standard is ratified next year, the deployment of this new technology will depend on the tools available to ease the development for chip designers, downstream board and system designers as well as manufacturers," said Stephen Lau, emulation technology product manager, Texas Instruments (TI). "ASSET's contribution has been invaluable to ensure that the IEEE 1149.7 will fulfill its promise of efficient and effective board and system test that was first offered in the original IEEE 1149.1 standard."

ASSET InterTech - Driving Embedded Instrumentation

ASSET InterTech is a supplier of open tools for embedded instrumentation to engineers doing design validation, test and debug. The ScanWorks platform provides automation, access and analysis tools in one environment. Users can quickly and easily validate and test semiconductors, circuit boards or entire systems during every phase of a product's life, including design, manufacturing/repair and field maintenance. In addition, chips can be programmed in-system after they have been soldered to a circuit board. ASSET's MicroMaster product line employs CPU emulation technology to perform extensive functional test and diagnostic routines on circuit boards and chips, and to program logic and memory devices in-system at high CPU speeds. ASSET InterTech is located outside of Dallas, TX, at 2201 North Central Expressway, Suite 105, Richardson, TX 75080.

For product information, call toll free 888-694-6250, send faxes to 972-437-2826, direct e-mail to ai-info@asset-intertech.com or visit the company's Web site at www.asset-intertech.com.