DFT Analyzer
at a Glance
Speeds up a new product's time-to-market.
Reduces manufacturing and test costs by validating DFT features.
Composed of three tools: Checklist, Design Validation and Test Coverage Analysis.
Checklist ensures testability consistency across the entire organization.
Company-specific rules are easily added.
DFT Analyzer™!
DFT Analyzer, the industry's first and only JTAG design-for-test tool. DFT Analyzer allows your organization to…
- Discover test issues early in the design development stage
- Ensure that PCB designs are testable with boundary scan before the first prototype is built
- Alert design engineers to any deficiencies in the boundary scan test coverage
- Recommend design changes that can yield better test coverage before any prototypes are built
- Improve test coverage
DFT Analyzer benefits everyone in your organization.
Design Engineer
- Reduced PCB prototype debug time by identifying ‘opens’ and ‘shorts’ more easily
- Elimination of expensive prototype re-spins through JTAG’s ability to reprogram devices on the PCB prototype
Test/Manfacturing Engineer
- Validate JTAG Design for Test more quickly with DFT Analyzer
- Cut manufacturing test development time by using the output of DFT Analyzer as the basis for ScanWorks test development
Management
- Accelerate time-to market by validating JTAG Design for Test
- Eliminate schedule delays through better test coverage
- Reduce manufacturing costs by alerting design engineers to any deficiencies in the boundary scan test coverage
DFT Analyzer is made up of three tools which are employed at different stages in product development. First, as schematics are being developed, DFT Analyzer’s automated Checklist queries a designer or test engineer about the testability features included in a design. These questions are based on sound DFT principles derived by ASSET from its many years of working with board designers to optimize boundary-scan test coverage. In addition, design practices specific to the organization can be included in the Checklist to ensure consistency across all of a company’s designs.
Next, DFT Analyzer’s Design Validation tool can be launched after computer aided design (CAD) information has been compiled. With the CAD data that is imported into DFT Analyzer, the Design Validation tool determines whether any pre-established DFT rules have been broken or overlooked. The tool recommends solutions if it encounters a broken rule. Company-specific DFT rules can be added to those already included in DFT Analyzer. New rules are defined in C# programs.
DFT Analyzer’s third tool, Test Coverage Analysis, is engaged during the final stages of design before first prototypes of the board are manufactured. This tool determines the extent of boundary-scan test coverage when certain types of tests, such as interconnect, memory and others, are run on the circuit board. In addition, the report contains information concerning which ICT test points can be eliminated by substituting a boundary-scan test for the ICT process. Eliminating ICT test points saves board space and reduces the complexity and cost of ICT test fixtures. In addition, the Test Coverage Analysis module can output results to the DFT Analyzer’s design browser which graphically displays the available test coverage in a schematic view.
The final output of DFT Analyzer is a complete boundary-scan description of the design that can be imported directly into the ScanWorks test-generation engine. A comprehensive suite of boundary-scan tests can then be generated and optimized for the first prototype boards. Subsequently, this JTAG test suite can be re-used through the manufacturing process as well as system test and field support.
To learn more about DFT Analyzer, talk to one of our experts...
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