How Can Boundary Scan Help Things You Do?

Test Development

Flash Programming

CPLD/FPGA Programming

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Test Development

PROBLEM

First, end users continue to increase their demand for more functionality in smaller packages. When these requirements ripple through to the printed circuit board level, it means that engineers have to put more devices into a smaller space. As a result, allocating space on the board for test points is becoming an unaffordable luxury.This causes the second major factor, which is a move to new packaging technologies that no longer provide the physical access required to test devices and boards using conventional technologies, such as in-circuit testers.

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SOLUTION

DFT technologies, like boundary scan (also known as JTAG) solve these problems. Other DFT technologies include BIST (Built-In Self-Test) and embedded ATE (Automated Test Engineering). Boundary scan is critical to these technologies, because it provides access to the device, board or system -- to enable these test methodologies.

If you would like to implement DFT, ASSET can help you make it happen. To get started with boundary scan, we recommend that you consider a solution including some combination of the following three elements:

To speak with an ASSET representative, click here.

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Flash Programming

PROBLEM

Flash programming refers to the ability to program or reprogram a Flash memory device after it has been soldered onto the printed circuit board. This is also referred to as "on-board programming". Typically flash devices hold the code that is executed by the processor or micro-controller to run a system.

Flash programming offers tremendous benefits to companies, because they can manufacture boards or entire systems in volume -- and have the flexibility to go back later to configure the devices to suit any application a customer requires.

This allows for more efficient manufacturing, and lowers the cost of keeping a variety of different parts (which are all the same, except for the way they are programmed) in inventory.

Flash also simplifies the process of responding to Engineering Change Orders (ECO) or Engineering Change Notices (ECN), since reprogramming a flash device can modify a board for a new use simply.

The problem arises for design engineers in developing prototypes, because they must program the device many times during the debugging process as the processor code is developed. With today's advanced packaging options, such as BGA's or chip-scale packaging, older methods that relied upon socketing the Flash and using some type of stand-alone programmer are becoming unusable, in terms of physical damage to the board, or expensive, in terms of wasted devices and sockets. Increasingly, designers require the ability to program a flash device after it has been attached to the printed circuit board. In a manufacturing setting, engineers have a similar problem -- with an additional complication. Conventional testing methodologies (like in-circuit testers) lose their usefulness when direct access to the flash device is not available.

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SOLUTION

Using ASSET JTAG, boundary-scan tools, engineers are free to solder flash devices onto a printed circuit board and program (and reprogram) them as many times as they want -- without ever touching the device.

Boundary scan can do on-board programming by using the boundary-scan structure of the adjacent microprocessor.

If you would like to get started programming flash memory with PC-based boundary-scan tools, we suggest that you combine the following three elements:

To speak with an ASSET representative, click here.

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CPLD/FPGA Programming

PROBLEM

In-System Configuration (also known as In-System Programming (ISP) or on-board programming) is the process of programming CPLDs (complex programmable logic devices) after they have been soldered to a board. ISC is accomplished using tools provided by programmable device vendors, on ATE/ICT testers, or by PC-based tools designed for boundary-scan test such as ASSET.

Device-vendor tools support only devices from that vendor and have limited scan path management support. Each tool has a unique user interface to learn and a unique connection to the board. These tools use the PC parallel port for access to the board. As a result, designs that use more than one device type require you to switch between vendor tools to program each device type.

ISC with ATE/ICT allows ISC to be integrated with test operations, but it is expensive. Time on ATE/ICT systems can cost as much as $1.00 per second and programming times typically range between 5 seconds and two minutes. Programming file sizes for ATE/ICT can also be very large, exceeding the capability of the testers.

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SOLUTION

Implementing ISC with ASSET PC-based tools solves many of the problems associated with your other options. This is a universal solution, supporting devices from all major vendors via one user interface and one connection to the board. This also allows the integration of ISC and test on a low cost test platform (typical costs - $0.05 per second).

With its sophisticated scan path management capabilities, ASSET provides safer scan path integrity testing and is able to maintain a board state that is safe for programming. It also enables ISC across complex scan paths such as system backplanes. Finally, using hardware optimized for boundary-scan application enables significant reduction in programming times. If you would like to get started implementing ISC with PC-based boundary-scan tools, we suggest that you combine the following three elements:

To speak with an ASSET representative, click here.