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PROBLEM
Design engineers have to test not only
their own designs, but also the early prototypes that come back
from manufacturing. The project can't move forward until the prototypes
coming out of both design and manufacturing are "known good."
In a new product's prototype design phase,
engineers are typically confirming that the devices function as
intended, and that the projected means of attaching devices to
the board work as planned. Soon after, when the first few boards
come back from manufacturing, it's critical to test for solder
smears, bridges and gaps, plus misplaced and defective parts.
Under ideal circumstances, an in-circuit
tester (ICT) can be used to perform the necessary tests (functional,
structural, interconnect). But this becomes a problem if the fixtures
for the ICT haven't been developed yet -- and typically this doesn't
happen until a board is "known good." This leaves a design or
test engineer only the options in his lab -- standard instruments
and visual inspection. However, advanced packaging technologies
are reducing the usefulness of these options, by limiting or removing
physical access to the device, board or system.
SOLUTIONS
JTAG tools from ASSET solve this problem by giving prototype
designers the ability to generate, conduct and evaluate a full
range of tests. Tests can be done at any stage of the product's
development, in any location, at any time of the day (or night).
And the process is simplified because to run a test, all you have
to do is hook the device, board or system to a PC.
Boundary scan aids in design verification by allowing an engineer
to:
- Program boot code in a flash device,
to initialize the system
- Put design configuration data into
a CPLD
- Gain access to internal structures
of an ASIC
- Initialize board state or capture
the board state for analysis (in a PC file)
In these ways, ASSET boundary-scan tools help engineers find
defects and verify designs.
To
speak with an ASSET representative, click here.
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