PROBLEM

First, end users continue to increase their demand for more functionality in smaller packages. When these requirements ripple through to the printed circuit board level, it means that engineers have to put more devices into a smaller space. As a result, allocating space on the board for test points is becoming an unaffordable luxury.This causes the second major factor, which is a move to new packaging technologies that no longer provide the physical access required to test devices and boards using conventional technologies, such as in-circuit testers.

SOLUTIONS

DFT technologies, like boundary scan (also known as JTAG) solve these problems. Other DFT technologies include BIST (Built-In Self-Test) and embedded ATE (Automated Test Engineering). Boundary scan is critical to these technologies, because it provides access to the device, board or system -- to enable these test methodologies.

If you would like to implement DFT, ASSET can help you make it happen. To get started with boundary scan, we recommend that you consider a solution including some combination of the following three elements:

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