SEARCH:
 
SERVICES MENU

 

EDFT Services Overview

Partner Provider

BSDL Validation

DFT Lab

Test Development

Consulting

 

 
CASE STUDIES

QLOGIC

See how ASSET helped Qlogic find the best boundary-scan test and in-system programming environment available.

 

ODS NETWORKS

See how ASSET helped Raytheon and ODS reuse their tests as they moved from development to manufacturing.

 
How to Reach Us

EDFT is located at 2201 N. Central Expy., Suite 105 Richardson, TX 75080

 

For more information about the Partner Provider, send an email to: ai-info@asset-intertech.com

 

ASSET currently offers two services to validate the accuracy of Boundary Scan Description Language (BSDL) files that characterize the boundary-scan functionality of semiconductor devices. One service validates a device’s BSDL file while the chip is still in development. The second service verifies the accuracy of a BSDL file against actual silicon.

The quality of these BSDL files is essential to improving the testability of printed circuit boards and systems for hardware manufacturers. When a BSDL file is inaccurate or the implementation of boundary-scan in a device is poorly executed, testing or programming the device will require additional time and effort to troubleshoot. Moreover, in the worst case, an inaccurate BSDL file will reduce boundary-scan test coverage in every product where the device is designed-in.

BSDL Validation Service

ASSET and Agilent Technologies, Inc. have jointly developed a new online service that performs BSDL validation. This free service syntactically and semantically checks the file, confirming correct spelling, punctuation, instruction codes, register associations and register cells, as required by the 1149.1 standard. It also automatically generates test patterns, creating a set of test vectors in a simple truth-table. These vectors can effectively test a chip design during the simulation phase to verify that it meets many of the requirements of the IEEE 1149.1 boundary scan standard.

To access BSDL Validation Service, click here.

BSDL Silicon Validation Service

Once a BSDL file has been syntactically and semantically validated and first samples of the semiconductor device have been produced, the accuracy of the file can be verified against actual silicon with ASSET’s BSDL Silicon Validation Service. The silicon is sent to ASSET and placed in a fixture that provides proper power and ground, boundary scan access to each I/O, access to TRST, TMS, TCK, TDI and TDO, and static control of compliance enable pins. Then a test sequence is generated for the device/BSDL consisting of:

  • RESET Action
  • DR Verify Action
  • Scan Path Verify Action
  • Device ID and Bypass DR Scan only
  • IR Capture
  • Bypass Register
  • IDCODE
  • Boundary-scan Register Length
  • USERCODE (if applicable)
  • Interconnect/Pin Test

Click here to view a Statement of Work for 1149.1 BSDL Silicon Validation.

Click here to view a Statement of Work for 1149.6 BSDL Silicon Validation.

Why Validate? Click here to read a Horror Story...

For more information on the BSDL Silicon Validation Service, please click here.

 

Free Hit Counter Code