Connecting the dots:
Global recovery, Moore’s law, chip packaging and test

By Glenn Woppman
President and CEO
ASSET InterTech

Recessions are no fun, especially global recessions. But recent glimmers at the end of the economic tunnel are encouraging. And if statements by an analyst at Gartner Inc. prove prophetic, the industry will be facing some tough test issues simultaneous with the rebound.

Semiconductor International quoted Jim Walker, vice president of semiconductor manufacturing research at Gartner, as saying, “Out of the downturn, we’re rapidly shifting from 2D to 3D packaging…We’re stacking packages, wafers, die, and even seeing through-silicon vias (TSVs) start to take off as well. Even though package and die stacking have been around for a few years now, as we come out of this downturn we’re going to go from 2-D to 3-D in a big way…”

Walker claimed that there’s historical precedence for this. Following the downturn in 1985, surface mount technology displaced through-hole and dual inline packages (DIP) migrated to the more compact small outline integrated circuit and plastic leaded chip carrier (SOIC/PLCC) packages. Then again after the 2001 recession, leadless and chip scale packages like ball grid arrays began to take off. The new packages transformed the products the chips went into, according to Gartner’s Walker. He asserted that we can expect another migration soon, except this time we’ll be talking about 3D chip packages.

Why 3D?

3D chip-building techniques have been around for several years, because, if the industry is to continue to follow Moore’s law (doubling on-chip transistors every two years), then 3D chips offer a viable means of doing so. Solid State Technology magazine, in an article reporting on a SEMATECH workshop more than a year ago, said that shrinking chip geometries to 32 nanometers (nm) and smaller would involve “physics constraints (that) will force so many changes in materials, processes and device structures that even if solutions could be found, they may be very expensive and time-consuming to develop and put into production fabs.”

A keynote speaker at the SEMATCH workshop, Phil Garrou of Microelectronics Consultants of North Carolina, pointed to a bonded processor/memory stack for a video console as an example of how a 3D chip can postpone a shift to a smaller geometry. In this case, the processor/memory stack allowed the manufacturer to stay at the 90 nm node rather than moving to 65 nm.

Working the Kinks Out

Despite the fact that significant progress has been made on the fabrication technologies needed for 3D chips, there are still some bumps in the road ahead. Test tools may be one of those bumps, but progress is being made on this front too.

The crux of the test challenge for 3D chips is access. Or, more accurately, an absence of access is at the heart of the matter. Stacking several silicon die on top of each other could seal off one or more die from external access via any test technology based on a physical probe. Chip manufacturers have recognized this and they are embedding various types of test and measurement instruments into their cores so that the chips themselves will be able to engage these instruments from the inside out, so to speak. These embedded instruments would monitor conditions on the chip, gather data and report results to an external test platform like ScanWorks.

Fortunately, several new IEEE standards are in the works and they will go a long way toward creating the kind of open environment that is needed for the development of third-party tools. These new standards are IEEE 1149.7, an enhancement and derivative of the original IEEE 1149.1 boundary-scan standard, and IEEE P1687, the so-called internal JTAG (IJTAG) standard. By the way, ASSET’s Adam Ley, chief technologist-boundary scan, has served on the 1149.7 working group and compiled much of the test content in the standard. Another ASSET leader, Al Crouch, chief technologist-core instrumentation, is co-chairman of the IEEE P1687 working group. More in-depth information on both of these standards is available in this issue of Connect. Click here to go to an article by Adam on 1149.7 or click here to go an article by Al on P1687.

These two standards as well as others that have already been adopted by the industry signal the emergence of an ecosystem of standards which will create an open environment where third-parties like ASSET can develop the tools that are needed for 3D chip testing. The figure below shows how several standards will interplay with each other in this ecosystem.

ASSET’s architectural view of 3D chip access and testing
Click here to enlarge

The illustration above is a 2D rendering of a 3D concept. To imagine this diagram in 3D, think of several of these 2D illustrations stacked on top of each other. Each silicon die in the stack would have boundary-scan cells along the perimeter. In this case, a two-wire 1149.7 interface is used on the device to reduce chip access costs. The internal 1149.7 architecture is a star. Although it is not shown in this illustration, the star architecture can be extended to die underneath the die in the block diagram with through-silicon vias (TSV). 1149.1 Test Access Ports (TAP) front-end each core’s IEEE 1500 wrapper so each core can be treated as if it were a chip with a JTAG port. Each core also contains one or more embedded instruments for test and measurement purposes and which conform to the IEEE P1687 standard. By conforming to P1687, all of these instruments can be accessed, automated and managed from a single test platform, which can analyze the instruments’ output. Also shown in this block diagram is the fact that these standards can be compatible with proprietary embedded instrumentation. Intel®’s embedded instrumentation technology, Interconnect Built-In Self Test (IBIST), is shown on the periphery of the die where it can be utilized for SerDes BIST testing and validation.

More to come….

Obviously, I have covered a lot of ground in very broad strokes. Suffice it to say that future issues of Connect will bring you much more information about the evolution of tools for testing 3D chips before and after they’ve been installed on circuit boards. You can be assured that ASSET will be one of the pioneering companies in this field.