New IJTAG standard will generate millions for chip and system manufacturers

By Al Crouch
Chief Technologist—Core Instrumentation

The new IEEE P1687 IJTAG standard holds tremendous economic promise for chip and system manufacturers, and users too for that matter. The standard, following its ratification and promulgation throughout the industry, will save manufacturers considerable costs, but it will also indirectly generate revenue as well. And users could benefit from lower price tags and higher quality products.

P1687 or IJTAG is an optimizing technology for the many types of test and measurement instruments that are currently being embedded into semiconductors. The reasons for embedded instrumentation are many. For the chip makers the rationale revolves around cutting development and manufacturing costs, and generating more revenues by bringing new technology to market faster, which results in seizing market share away from the competition.

At the 90 nanometer (nm) process node, chip manufacturers face development and production costs for making a set of fabrication masks in the neighborhood of $400,000 to $700,000. At smaller nodes, the costs escalate considerably. It’s at least $1 million at 65 nm and between $2 and $2.5 million at 45 nm. The more comprehensive testing capabilities provided by embedded instrumentation will lower these costs by detecting more of the faults and failures earlier in the development cycle. This will reduce the number of design spins, which reduces the production of successive sets of masks. In the end, chip manufacturers want to ramp to volume production as quickly and easily as possible. In Figure 1 below, m1, m2, m3 and m4 represent additional sets of masks which delay volume production and run up pre-production costs.

Figure 1 - click here to enlarge

Chip yield is another concern that embedded instrumentation addresses. As Figure 1 indicates, lower than expected yield during volume production reduces production volumes and, as a result, brings down total revenues from the chip. As Figure 1 indicates, this can bring the revenue and cost lines perilously closer together. When revenue dips below costs, the chip manufacturer typically ceases production of the device. A mere 10 percent drop in yield over the course of a month on a high volume device can cost a manufacturer several million dollars. Instruments embedded into these devices are being used to improve yield rates by quickly identifying faults in manufactured chips and rapidly diagnosing their causes. Providing this information on a timely basis allows chip makers to adjust their manufacturing processes faster and keep yield rates high.

Chip yield becomes even more critical and costly when a 3D chip with multiple die in a single package is being assembled. (For an article on 3D chip testing in this issue of Connect, click here.) With a single-die device, for example, a failure rate of one in 10 die is a 90 percent yield or a 10 percent loss rate. If three die are placed in a 3D chip and each of the die have a 10 percent loss rate, then the 3D device could also have a 10 percent loss rate. But, the three in 30 3D devices that fail will cause another six good die to be thrown away. That’s a 30 percent yield for all 30 of the die in the 10 3D packages. A slightly worse yield on the individual die further degrades these numbers. For example, if each individual die family has a 70 percent yield, then the yield on the 3-die stack could theoretically become a mere 10 percent. (See Figure 2 below.)

Figure 2 – Multi-die chip yield can degrade quickly.
Click here to enlarge

Of course, the clock is always ticking on time-to-market. As Figure 1 shows, the typical lifetime in the marketplace for most high volume semiconductors can be anywhere from eight months to three years. Better test through embedded instrumentation means fewer design spins, faster analysis to keep yields high and shorter cycles all around. All of that means that the device will be in the market sooner and generating more revenues for the supplier than if it were late to market.

Given these and other economic benefits, it’s easy to understand why chip companies are embedding more and more instruments into their devices. Still, effective access mechanisms and open test tools for embedded instrumentation will optimize their ROI for chip makers and system manufacturers.  That’s where the IJTAG standard comes in.

Optimizing Embedded Instrumentation

Over the last decade or so, the electronics industry has moved to higher and higher levels of integration at the chip level. In fact, much of chip design today centers on the integration of multiple intellectual property (IP) cores into a system-on-a-chip (SOC). Having hundreds of cores, each with its own set of embedded instruments, on an SOC complicates considerably the deployment of embedded instruments in effective test strategies. The recent ascent of 3D device packages, like system-in-chip (SiP) or package-on-package (PoP), complicates matters even further.

The P1687 IJTAG standard addresses this situation. Specifically, the standard provides an effective way to access and manage embedded instrumentation. Access protocols for embedded instruments can vary according to the source of the core and/or the instrument. The chip’s manufacturer could have its own protocol for accessing its embedded instruments while core IP vendors have another. And in-house design departments likely prefer their own access methods. With such a diverse array of access methods, it is very difficult to develop cohesive test strategies, especially when there may be thousands of embedded instruments on one SOC, SiP, PoP or circuit board.

The IJTAG standard offers a common and open access method for all embedded instruments no matter where they come from. Based on an access methodology consistent across all conforming embedded instruments, IJTAG enables better coordination, automation and management controls among the instruments. This translates into more effective and more cohesive test strategies at the chip, board and systems levels.

Another emerging standard, the IEEE 1149.7 Enhanced and Reduced-Pin Boundary-Scan Standard, also addresses the access issue and, to some extent, complements the IJTAG standard. Physically accessing the many instruments in multiple cores, or in multiple die in a 3D package, is difficult at best. At its worst, access can be exceedingly difficult. For example, one die in a multi-die 3D device could block external access to another die in the package.

1149.7 functions in conjunction with through-silicon vias (TSV) to provide physical access to embedded instruments. For a fuller description of 1149.7 click here for an article in this issue of Connect by Adam Ley, ASSET’s chief technologist – boundary scan and one of the main contributors to the 1149.7 standard.

Figure 3 below shows how P1687 IJTAG and 1149.7 might complement each other in a multi-core device. 3D chips could deploy the same sort of solution replicated on multiple stacked die and connected by one or more TSVs.

Figure 3 – ASSET’s architectural view for accessing
embedded instrumentation with P1687 and 1149.7.
Click here to enlarge

Payback Over the System’s Lifecycle

The dramatically improved testability enabled by embedded instrumentation, P1687 and 1149.7 does not cease at the chip or board levels. Because this testability is based on open industry standards, it extends throughout system development, assembly and manufacture, as well as the entire lifecycle of the end product. In fact, embedded instrumentation and the standards which enhance it will eventually have a major effect on the way field service and system maintenance is performed in the future.

Consider the example of a medical diagnostic system, such as a sophisticated CT scanner, in a hospital in a remote rural area. The complex multi-core and 3D chips that make up the system undoubtedly have many embedded instruments in them. These instruments were originally embedded in the system’s components by chip manufacturers to perform chip-level test, debug and yield analysis. But later, after the CT scanner has been installed in a hospital or clinic many miles removed from a support center, these same instruments could monitor the system’s operations and output valuable diagnostic information in the event of a failure. The embedded instruments could transmit data to a remote field engineer who is working with the diagnostic tools on an open platform for embedded instrumentation such as the ScanWorks platform many miles away. Based on the data provided by the embedded instrumentation and the diagnostic tools available to the field engineer, a malfunctioning CT scanner could be returned to service much sooner and possibly save lives that might otherwise be endangered.

Delivering on the Economic Promise

The new IEEE P1687 IJTAG standard as well as complementary standards like the IEEE 1149.7 enhanced reduced pin-count standard are critical next steps that will certainly maximize and extend the ROI and economic payback of embedded instrumentation. In the future, embedded instrumentation will only increase in importance. Some in the industry have said that the higher levels of integration represented by 3D chips will be the most effective way for the industry to follow the trajectory of Moore’s law and continue doubling the circuitry on chips every two years. (See Glenn Woppman’s “Observations” column in this issue of Connect.) In any event, the complexity of chips will be astounding. Embedded instrumentation and its supporting standards will proliferate because they are needed and they will deliver on their economic promises.