Article details the emerging standards for 3D chip test

Al Crouch
Chief Technologist—Core Instrumentation

Al Crouch’s article on 3D chip test appeared in the Oct. 5 issue of the SOC Central newsletter and has been posted to the SOC Central web site (www.soccentral.com).

The article begins by pointing out that many experts and analysts believe 3D chip packaging will be an effective way for the industry to continue following Moore’s law and double the density of circuitry on chips every two years. Unfortunately, current chip test technologies cannot assure high yields on 3D chips. Fortunately, several industry standards and advances by test companies are providing a glimmer of light at the end of the tunnel.

A problem of access

A lack of access to the die in a 3D chip is at the heart of the test problem. One or more die will block access for any intrusive probe-based test technology to the other die in the package. Yield suffers. For example, if each individual die in a three-die package has a 70 percent yield, then the yield on the three-die stack could theoretically become a mere 10 percent. (See Figure 1 below.)

Figure 1 – Yield on a 3D chip package can quickly deteriorate.
Click here to enlarge

Several emerging IEEE standards address the issue of 3D chip test. These are IEEE 1149.7, the so called compact boundary-scan standard, and the IEEE P1687 internal JTAG (IJTAG) standard. Other more established standards also come into play, such as the original boundary-scan standard, IEEE 1149.1, and the IEEE 1500 Embedded Core Test Standard. Semiconductor companies are also embedding various test and measurement instruments into their devices to mitigate the loss of access to external instruments, to overcome the growing inadequacy of external test equipment and to improve testability. One example of this is Intel®’s Interconnect Built-In Self Test (IBIST), which that company has embedded into its next-generation devices.

The 1149.7 standard, which is expected to be ratified by the end of the year, enables a broadcast star architecture and is compatible with through-silicon vias (TSV). Both of these features will be critical to 3D chip test. P1687 is being developed as a way to connect, access, analyze and describe embedded instrumentation. Since embedded instrument IP (intellectual property) can come from a number of sources, such as chip suppliers, third-party providers, EDA tools or in-house design groups, P1697 will offer a standards-based interface to all conforming embedded instruments. IJTAG enables a number of embedded instrumentation functions that will improve the testability of a a single-die chip or multiple-die in a 3D package. For example, IJTAG would simplify the parallel operation of multiple embedded instruments.

Test Re-Use

The article in SOC Central points out that the die that will be stacked into a 3D chip will be tested individually before they are stacked. If these tests were portable and could be re-used again to test the assembled 3D package, the chip manufacturer would save considerably. 1149.7 and P1687 could be used in this sort of scenario. The block diagram below shows how the two standards could complement each other and enable test re-use.

Figure 2 –How a 3D chip could be tested with 1149.7
and P1687 IJTAG. Click here to enlarge

In addition to re-using tests during chip fabrication and assembly, these same tests could be re-used throughout the lifecycle of the end product. P1687 IJTAG is being developed to carry this out. The figure below illustrates how this lifecycle test flow could become a reality.

Figure 3 – Lifecycle test flow within the context of the
IEEE P1687 IJTAG standard. Click here to enlarge

The article concludes by noting that open industry standards have always provided the basis for markets to develop where multiple vendors innovate and compete with one another to provide the most cost-effective solutions possible. This certainly will transpire with regards to test tools for 3D chips.

Click here to read the complete article on SOC Central.