Non-intrusive tools solve a multitude of problems

By Eric Johnson
Product Manager
I/O Instrumentation

According to a recent article in EETimes, all a panel at DesignCon could do was lament the current situation with regards to validating designs with high-speed serial buses.

"As soon as you put a probe or fixture at the end of a channel, you are screwing up a measurement," Martin Miller, chief scientist of LeCroy, said during the panel. "Life was simple at 1 Gbit/s, but that's not true anymore."

He’s right, of course, but ASSET’s non-intrusive tools for design validation, test and debug are making life simpler once again.

The DesignCon panel was discussing how difficult it has become for engineers to validate designs that contain high-speed serial buses with transfer speeds above one giga-bit per second (Gbps). That includes PCI Express 2.0 at 5 GHz, the 6 GHz Serial ATA, Serial-Attached SCSI, USB 3.0 which has a goal of eight Gbits/s and others. (To read the entire article from EE Times, click here.

For Intel® designs, there is a solution, the ScanWorks® IBIST QPI Validation Toolkit. Of course, there are other problems that non-intrusive tools address and which are a part of the ScanWorks platform. These include:

• CPU emulation for functional test. Click here to learn more about the MicroMaster module for ScanWorks.
• Boundary scan for life-cycle test and diagnostics. Click here to read an article in this issue of Connect about our recent boundary-scan enhancements to the ScanWorks platform.

Validating Intel® QPI designs with ScanWorks

The ScanWorks QPI Validation Toolkit utilizes Intel’s IBIST (Interconnect Built in Self Test) embedded instrumentation technology in that company’s QuickPath Interconnect (QPI) architecture. IBIST instrumentation technology is embedded into Intel’s next-generation chips and chipsets. QPI is an architecture which features high-speed serial links for interconnections between chips.

As the panel at DesignCon noted, validating the design of a bus with transfer speeds in excess of 1 Gbps is expensive. When it’s not impossible, it’s problematic at best.

The ScanWorks IBIST QPI Toolkit is a turnkey validation solution containing software and hardware, customization services, training and product support. The tools in the kit include:

• Pattern Generation and Checking
• Bit Error Rate (BER) Testing
• Margining

A number of companies have already deployed the ScanWorks IBIST QPI Toolkit. In addition to support for QPI testing on Intel devices, ASSET supports the Avago QPI layer. The Avago QPI SerDes (serializer/deserializer) is compliant with Intel® IBIST technology and is being deployed in ASICs in high-performance server applications. The ASSET contract with Avago gives customers the ability to rapidly automate, access and analyze IBIST data generated by both Intel chips and Avago’s own SerDes.

We feel that the ScanWorks IBIST QPI Toolkit and the adoption of ScanWorks’ IBIST tools by our customers has, in a general sense, legitimized the concept of validating high-speed I/O buses with embedded instrumentation.

Tools Today!

The tone of that DesignCon panel might have been a bit more upbeat had the experts known of the ScanWorks IBIST QPI Toolkit. The pattern generation and checking, BER testing and margining tools can help engineers validate QPI designs today.

Pattern generation and checking provides a capable tool for validating the transfer of rudimentary test patterns across I/O channels and chip interconnects. With simple pull-down menus in a graphical interface, users can easily specify patterns, bit count and which links and lanes to test. A single lane can be tested, or ScanWorks can target all lanes on all QPI links concurrently. The result is a quick and easy test for determining bus connectivity and integrity.

The ScanWorks BER testing tools perform exhaustive testing with a large amount of data while accurately tracking total bit count and bit errors. A single lane or all links on a design can be testing simultaneously, accelerating the design validation process as well as exerting stress on the entire system to validate its performance and identify interdependencies. In addition, ScanWorks takes the guesswork out of running BER tests by providing a built-in calculator that estimates test execution times and confidence levels before a test is performed.

The easy-to-use pushbutton margining tools in ScanWorks generate text and graphical results for each high-speed channel. ScanWorks can perform full-eye analysis or a quicker cross margin test. The tool can identify relative receiver performance margins when voltage and timing offsets are introduced. Test set-up and execution is simple with the ScanWorks user interface. ScanWorks margining is an excellent tool for visually characterizing bus design integrity. Pattern generation and checking, BER testing and margining make ScanWorks a powerful and efficient toolset for validating the links in a QPI design.

Get Started Now!

Necessity and economics are moving the industry toward non-intrusive validation, test and debug tools, which capitalize on the embedded instrumentation that is increasingly becoming part and parcel of today’s advanced technology. Fortunately, the ScanWorks embedded instrumentation platform has the tools that are needed today so that technology can continue to advance.

And ScanWorks will be right there for the designers and test engineers with the embedded instrumentation tools and functionality that will be needed.

For more information on the ScanWorks platform with its IBIST QPI Validation Toolkit, click here.