DesignCon paper discusses validation with ScanWorks® and Intel®’s IBIST

A research paper developed by ASSET Application Engineer Stephanie Akimoff was presented at the DesignCon conference last month in San Jose, Calif. The paper explained how platforms can be validated using Intel®’s Interconnect Built-In Self Test (IBIST). IBIST is an embedded instrumentation technology that Intel is placing in its high-end chips and chipsets.

In addition to including some basic information on IBIST, Stephanie’s paper offers insight into a methodology for testing a system’s multiple high-speed serial bus links. It contrasts different validation results such as test coverage, test time and eye capture that were compiled by different test methods, including an oscilloscope and ScanWorks®.

The paper points out some of the limitations of traditional validation techniques and demonstrates the results achieved by ScanWorks. For example, a ScanWorks IBIST margin test can plot an eye diagram for all of the serial lanes in a link at the same time while an oscilloscope can only generate an eye diagram on one lane at a time. In addition, ScanWorks’ margin tests generate an eye diagram of what is seen by the receiver, whereas an oscilloscope can only capture an eye diagram at the point where the probe is connected to the link, typically on a via on the surface of a circuit board. From this point, the signal must still pass through multiple layers of the board, a socket, the solder balls on the underside of the processor and through the processor package itself before it reaches the receiver. That via on the surface of the board  is several layers of potential discontinuity away from the receiver. In contrast, ScanWorks’ IBIST margin tests capture an image of the signal that the receiver sees.

For more information on the ScanWorks platform’s IBIST QPI Validation Toolkit and to download Stephanie’s complete DesignCon paper, click here.