New 1149.7 enhances 1149.1 test access port, maintains compatibility for boundary scan
By Adam Ley
ASSET Chief Technologist
Boundary Scan
As a founding member of the P1149.7 Working Group, ASSET InterTech has been involved in the development of this emerging standard since its launch under the auspices of IEEE-SA. With the draft standard now out for its initial sponsor ballot, we can safely say that ratification is expected soon. It’s time, I think, to share some information about 1149.7 with ScanWorks users.
Since I have been the chief author of the test content in the draft standard, I can say with confidence that 1149.7 will not change radically how boundary scan (per IEEE 1149.1) is being used today. The two standards are completely compatible with one another. In fact, 1149.7 was carefully developed so that 1149.1 and 1149.7 could be deployed in the same system and on the same circuit board. This is accomplished by an 1149.7 adapter module (Figure 1) which is embedded in 1149.7 chips and maintains compatibility with 1149.1.
Figure 1
Future Features
Of course, the timing and availability of the new features and capabilities of 1149.7 will depend upon how quickly the standard is deployed in chips. This process may take several years, although some chip suppliers have been aggressively preparing for the passage of the standard. In fact, some semiconductor design, support and test companies, such as IPextreme (http://www.ip-extreme.com) and Globetech Solutions (http://www.globetechsolutions.com), already have available 1149.7 intellectual property (IP) and verification solutions.
The 1149.7 standard offers several new features and capabilities, such as the following:
When 1149.7 comes up, most people refer to it as a reduced-pin count interface. It certainly can and will be deployed as a narrow (two-wire) interface in some applications, but the standard also allows for wide (four/five-wire) implementation as well.
Many of 1149.7’s feature enhancements relate to software debug applications. We expect that over time these types of capabilities could be utilized through related technologies like the CPU emulation functionality found in the ScanWorks platform’s MicroMaster module.
- Architectural enhancements
Perhaps the most far reaching enhancements offered by 1149.7 relate to architectural enhancements that will allow the standard to be effectively deployed in multi-core systems-on-chip (SoC) and multi-die packages like system-in-package (SiP) and package-on-package (PoP). Unlike 1149.1 deployments that are limited to daisy-chain arrangements, 1149.7 enables a star architecture (Figure 2) which is more appropriate for SoCs, SiPs and PoPs.
Figure 2
In SoCs, the architectural enhancements of 1149.7 allow for the test and debug interfaces of each core to be consolidated onto a single 1149.7 interface at the package level. For example, each of the three cores in a SoC might have an eight-wire test/debug interface for a total of 24 signals on the SOC. Consolidating all three of these interfaces onto one 1149.7 interface reduces the number of pins devoted to the test interface for the SoC to two (narrow) or four (wide).
In multi-die SiPs or PoPs, the 1149.7 standard offers the advantage that it can be deployed effectively using through-silicon vias. Daisy-chaining multiple die in a 1149.1 architecture requires a costly connectivity layer or substrate for the package. An 1149.7 implementation would link each die through a via that simply vertically connects the 1149.7 interface on each die one to another. (Figure 3)
Figure 3
1149.7 Solutions
Because of its compatibility with the original 1149.1 boundary scan standard, the new 1149.7 standard will be supported by the ScanWorks embedded instrumentation platform. Users of 1149.7 will be able to take advantage of ScanWorks’ industry-leading boundary scan tools as well as the platform’s other embedded instrumentation capabilities such as CPU emulation for functional test and I/O validation tools for Intel®’s Interconnect Built In Self Test (IBIST) technology and QuickPath Interconnect (QPI) architecture.
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