ASSET and Cadence team up for better test of complex chip packages
ASSET and Cadence are collaborating to integrate ScanWorks’ embedded instrumentation capabilities into the Cadence Encounter Digital IC Design flow. As a result of the integration, design and test engineers will be able to more effectively embed instrumentation tools into complex system-on-chip (SoC) and system-in-package (SiP) devices, providing deep analysis and test of these chips.
The project kicked off immediately, following the ASSET admittance into the Cadence Connections partner program.
The Cadence Connections Partner Program is available to makers of third-party software products that complement Cadence solutions and further enhance industry interoperability. Membership in the Cadence Connections program provides ASSET with access to Cadence software, documentation and support capabilities to facilitate the integration of ScanWorks’ embedded instrumentation tools into Cadence’s IC design, test and diagnostic flows. Cadence’s leadership in board and SiP package design will be leveraged to address the growing challenges of SiP and multi-chip module (MCM) device testing and diagnostics. Initial applications will provide tools and flows that support the preliminary IEEE P1687 Internal JTAG (IJTAG) standard, which is defining how embedded instruments will be accessed, managed and automated.
“As chips become more complex, including not just one but several entire systems in a single package, the ability to analyze and test deep within the device creates enormous benefit,” said Steve Carlson, vice president of IC digital at Cadence. “The collaboration to integrate ASSET’s ScanWorks software is expected to provide an automated data acquisition and data analysis capability that fundamentally turns on the light for chip designer and test engineers.”
Alan Sguigna, ASSET’s vice president of sales and marketing, noted the convergence of chip and board test.
“We are seeing a rapid confluence of our technology with EDA systems, such as Cadence Encounter Test,” said Sguigna. “Our strategic emphasis on open embedded instrumentation tools for design validation, test and debug can accelerate the chip verification and test process and enhance yields. This is especially true for the denser chip packaging techniques such as complex SOCs, SiPs and package-on-package (PoP). Cadence’s end-to-end solutions and diagnostics leadership and our expertise in embedded instrumentation give our collaboration a head start on addressing these challenges.”
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