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P1149.7 promises reduced pin-count, enhanced
functionality IEEE 1149.7 standard
ASSET’s Adam Ley, chief technologist, has assumed a principal role in the development of IEEE 1149.7 as one of the founding members of the working group that is defining the emerging standard, which is expected to be ratified in early 2009.
Deriving from the established IEEE 1149.1 Test Access Port (TAP) and Boundary-scan Architecture standard, but offering options for a smaller, two-wire interface and enhanced functionality, IEEE 1149.7 extends the test and debug capabilities of the IEEE 1149.1 standard’s TAP to complex devices like system-on-chip (SOC), system-in-package (SiP), and other multi-core or multi-die devices. In its reduced  pin count form factors, IEEE 1149.7 has been targeted for mobile products, but it offers enhanced test functionality for any electronic system.
“Advanced semiconductor devices today are packing the capabilities of entire systems into one device. In fact, SOC and SiP technologies are becoming more and more prevalent,” Adam explained. “By participating in the development of IEEE 1149.7, we intend to simplify the access, automation and analysis of embedded instrumentation through the standard test access port, just as we have done for the IEEE 1149.1 boundary-scan standard, and as we are doing for another emerging embedded instrumentation standard, IEEE P1687 (also known as Internal JTAG or IJTAG). In fact, we view all of these standards as complementary and synergistic.”
“Once the standard is ratified next year, the deployment of this new technology will depend on the tools available to ease the development for chip designers, downstream board and system designers as well as manufacturers,” said Stephen Lau, emulation technology product manager, Texas Instruments (TI). “ASSET’s contribution has been invaluable to ensure that IEEE 1149.7 will fulfill its promise of efficient and effective board and system test that was first offered in the original IEEE 1149.1 standard.” |
