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Chip learns a lesson from Mr. PCB
Strolling casually into a San Jose Starbucks recently, Dave Bonnett, ASSET’s roving Product Manager, unintentionally overheard a heated conversation between the well known hardware test engineer and circuit board aficionado, Peter C. Bennetts, who in friendly circles goes by the moniker of PCB, and a young semiconductor designer named simply Chip.
[Editor’s Note: Chip’s last name is being withheld to protect the guilty.]
The two were at odds – you might even say there was contention between them – over the absence of a consistent design and test methodology in the semiconductor industry for 1149.x implementations within components. Our man Dave furiously scribbled down notes while PCB and Chip were going at it. Because of the ferocity of the conversation, we can not attest to the absolute veracity of Dave’s notes, but we think he caught the most important bits and even a few bytes while he was at it.
Here’s how the scene unfolded:
PCB: “Listen Chip, you just don’t get it, do you? If I’ve told you once I’ve told you a thousand times; when you do a crummy job of JTAG insertion, who ends up paying the price? I do!”
Chip: “I guess you’re right, but I don’t see that it’s something to get all worked up about. Everyone tells me that JTAG is for emulation. And we use it a little bit in the lab as a convenient way to access embedded instrumentation. But I don’t know of anyone at all who uses the boundary register. So, my question to you is, why should I even include boundary scan? And if I don’t, what’s the difference to you?”
PCB: “Well, you haven’t been keeping up with the times, Chip. JTAG as a technology has advanced so far that it is being used in tons of applications, within a variety of functions, from design right through the entire product lifecycle to field repair. Just to enlighten you, let me list some of the applications of boundary scan.”
[At this point, PCB begins emphatically counting off his points on his fingers.]
- “First, there’s board test – looking for shorts and opens.
- Then there’s flash programming.
- And how about CPLD configuration?
- Next, emulation support.
- And now signal integrity validation – with embedded instrumentation like Intel®’s IBIST technology – is becoming extremely important.
- Then there’s prototype development and debug.
- And how about manufacturing test? Tried any of that lately, Chip?
- Of course, you could use JTAG to do debug and repair more efficiently. That is, if it worked properly.
- And software engineering would find it useful.
- And here’s something you might be interested in, chip testing with boundary scan.
“Do you want me to go on? I can, you know.”
Chip: “No, no, I hear what you’re saying, but a lot of this stuff looks like test to me. I’m a designer. It just doesn’t seem all that important to me. My job is to make chips that work. Chips that function to spec. That goes for microcontrollers, DSPs, FPGAs, custom chips, whatever the device is. So what’s the big deal if some of the test functionality isn’t the way it’s supposed to be? If the chip works, who cares?”
[Suddenly, PCB’s face turns a bright fire-engine red. It’s obvious he’s agitated by what he’s just heard.]
PCB: “You slay me, Chip; literally, I might add. You really need to get in touch with your customers! Haven’t you heard about the latest semiconductor design fiasco at XXXXXXX ? [For purposes of national security, or at least to save Chip’s job, this document has been redacted by an unnamed agency of the electronics industry. The names of the complicit companies and individuals have been blacked out.] They built a DSP that a very large aerospace account was going to deploy in thousands of boards. But after going through some engineering samples, the aero guys found that the JTAG implementation on the chip simply didn’t work! And you know what? They couldn’t test their prototypes. They figured that it was going to cost them a huge amount of money to revamp their board test methodology and deploy in-circuit test instead of boundary scan test. They were so upset that they cancelled the order and went with a competitor’s DSP that had designed JTAG correctly on the chip. The whole thing cost XXXXXXX a $20 million order. That’s a pretty costly mistake, I’d say!”
Chip: “Wow, I hadn’t heard about that one…sounds serious.”
PCB: “Yeah, it was and it gets worse! You probably haven’t heard about XXXXXXX, the guy who designed a chip that required an elaborate JTAG power-up sequence. It went something like: set this pin high; then, within 50 milliseconds, set another pin low and then wait 200 milliseconds before applying a 30MHz clock to a third pin. And then a reset would be sent out from the core logic to the TAP pins during the transition from SAMPLE to EXTEST, causing the scan chain to break…Anyway, you get the idea. XXXXXXX lost another big chip order because of that one.”
Chip: “My oh my, I didn’t realized things were that bad out there…”
PCB: “Yeah, well, just remember these two words: liquidated damages. You know what they are? Well, the news is all over the Valley about XXXXXXX, who signed a big contract for microcontrollers, but built in a clause that there would be a $5 million “holdback” if JTAG didn’t work properly on the device. Guess who ended up paying?”
Chip: “Ohmygosh, I never knew this was happening…”
PCB: “Okay, let’s get down to brass tacks. I think that I’ve convinced you that this stuff’s important, right? [Chip nods his head in agreement.] Now, I’d like to know how you verify and validate that your device has implemented JTAG correctly, both pre-tapeout and post-tapeout. Here’s a little quiz:
“Do you syntactically and semantically validate your BSDL file with the ASSET/Agilent BSDL Validation Service atwww.asset-intertech.com/bsdl_service?”
Chip: [At this question, Chip, who has been looking pretty glum, brightens a little.] “Yeah, I sure do! And the BSDL files for my devices always pass.”
PCB: “That’s good, but I’m sure you know that this only verifies syntax and semantics, and it doesn’t guarantee that the BSDL matches the silicon or that the silicon works correctly. I’m sure you knew that, didn’t you, Chip? By the way, how do you do your JTAG design insertion? Do you use Mentor’s BSDArchitect, LogicVision’s ETBoundary, or something similar?”
Chip: [Chip appears crestfallen.] “Well, um, not really. All this boundary scan stuff is usually the same; so, we just do it by hand. We insert all the JTAG logic by hand.”
PCB: “Well, if that’s the case, do you verify it on a testbench? Do you, for example, use the vectors generated from the ASSET BSDL validation service on the Web to independently verify your design in simulation?”
Chip: “Um, no.” [The forlorn look on Chip’s face indicates a defeated man.]
PCB: “I’d say you’re not really going to be all that confident that the JTAG in your design is going to work. Do you at least validate the silicon? With something like ASSET’s post-tapeout BSDL Silicon Validation service, once you’ve got early chip samples?”
Chip: “Errrr, no, we don’t. We figure our customers will let us know if there’s a problem.”
PCB: “Great plan, Chip! Good way to keep those customers happy! [At this point PCB has regained his composure and looks rather smug. A wry smile flits across his face.] You know, by the time your customers have found your mistakes, it’s too late. [Chip nods, thoroughly vanquished.] There are a bunch of guidelines you need to follow to ensure your device is compliant with IEEE 1149.1. Let’s go over them, one by one. Now, repeat after me….”
[At this point PCB shot off a list of critical JTAG compliance features. Dave wrote furiously and got most of them. Watch for the next issue of Connect where this story continues with a complete list of compliance features.]
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