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The IEEE P1687 (IJTAG) working group has been busy developing a preliminary hardware proposal document describing the architectural rules for the draft standard’s embedded instrumentation as well as some of the draft standard’s basic concepts. The hardware proposal has been posted to the IEEE P1687 web site (click here) for review by its members and the industry in general.

The chief editor of the hardware proposal is Al Crouch of Inovys Corporation and vice-chairman of the IJTAG working group. Appreciation is owed to Mr. Crouch for providing the figures contained in this article.

JTAG/IJTAG Architectural Concepts

A P1687 instrument is defined as any embedded logic (exclusive of 1149.1/JTAG/boundary-scan board-test logic that may be present) within a chip for test, debug-diagnostic, configuration or operational purposes, and which can be accessed and operated from within the P1687 framework. Examples of P1687 instruments are scan architectures, memory BIST engines (Built In Self Test), logic BIST engines, clock-controllers, data capture buffers and embedded logic analyzers.

The conceptual architecture described in the draft hardware proposal delineates three basic partitions: the boundary scan/JTAG infrastructure as seen from the circuit board and known as the 1149.1-Zone, a transitional gateway zone which is referred as the 1149.1 Overlap Zone in the hardware proposal and which interfaces the 1149.1-Zone to the third or instrument zone, which is called the P1687-Zone.

The transitional elements in the 1149.1 Overlap Zone act as bridges between 1687/IJTAG instruments and the 1149.1/JTAG/boundary scan Test Data In (TDI) – Test Data Out (TDO) serial data path and Test Access Port (TAP) controller. Facing the P1687 Zone, these gateways enable board-level access to embedded IJTAG instruments from the 1149.1 TAP.

The 1149.1 Overlap Zone described in the IJTAG Hardware Proposal conforms to the IEEE 1149.1 Boundary Scan Standard, including the TAP and TAP controller, but uses private instructions for accessing P1687 gateways. Gateways in the 1149.1 Overlap Zone de-couple the 1149.1 Overlap Zone from the P1687 Zone so that the P1687 Zone is not limited by the need for 1149.1 compliance. A “gateway enable” (GWEN) JTAG instruction selects, configures and enables P1687 gateways. A P1687 gateway can be an instrument in its own right, but it also enables a hierarchical connection to another embedded instrument for which it acts as a gateway. This hierarchical gateway connection involves passing JTAG’s TDI-TDO signals and a local select signal to subsequent instruments.

The P1687 Zone features embedded instruments as well as an IJTAG Alternate Controller(s), if required. An Alternate Controller is a conversion element that allows any non-compliant instrument to conform to the four defined IJTAG instrument types so the non-compliant instrument can be controlled from the 1149.1 TAP Controller. Alternate Controllers can create control signals for just one instrument, groups of instruments or signals that are global to the entire P1687 Zone. Conceptually, the Alternate Controller can create control sequences which are not compliant with the 1149.1 TAP but are required by certain types of complex instruments such as sophisticated IEEE 1500 core wrappers that use non-1149.1 sequences, a clock other than the clock defined by the 1149.1 Test Clock (TCK), or a data path other than the 1149.1-defined TDI-TDO serial scan path. In addition, high bandwidth input/output (I/O) ports can be deployed by an IJTAG device in the P1687 Zone.

Archetypal Instruments

At this stage in the development of IJTAG, the preliminary P1687 hardware proposal defines four different classes of archetypal embedded instruments. They are the following:

Type B instruments operate identically to an 1149.1-defined test-data register. They have a serial path and the hierarchical connection(s) needed to act as a gateway element. As a gateway, Type B instruments have some restrictions caused by the need for BSDL to describe registers as fixed-length registers.

An example of a Type B instrument would be any instrument that is directly managed by 1149.1 state-machine signals and associated boundary scan’s Select-Capture-Shift-Update protocol.

This type of IJTAG instrument conforms to the wrapper and control mechanisms which are compatible with the JTAG IEEE 1149.1 boundary-scan standard and which are defined in IEEE 1500 Standard. (Note: not all 1500 structures are compatible with 1149.1. See Type D instruments below.) Type C instruments have one or more serial scan paths and thus support the hierarchical connectivity required to function as a gateway. One of a Type C instrument’s multiple registers is defined as an Instruction Register (IR) and, as a result, a Select-IR signal is required.

An example of a Type C instrument would be a 1500-wrapped core with core boundary-scan cells that do not require the auxiliary ‘transfer’ signal.

Type D instruments have at least one control interface signal or sequence that cannot be driven by the IEEE 1149.1 TAP controller. Complex Instruments can not be used as gateways because they can not be easily described by BSDL, which is a requirement of being a gateway in the 1149.1 Overlap Zone, but they can be connected to other elements in a hierarchical arrangement.

An example of a Type D instrument would be a 1500-wrapped core with core boundary-scan cells that require the auxiliary ‘transfer’ signal or which operate using a system clock other than the 1149.1-defined TCK.

The four archetypal P1687 instruments are illustrated in the figure below:

It should be noted that the P1687 hardware proposal does not require that all instruments embedded in a single component comply with P1687. The proposal document discusses several conversion options for non-P1687-compliant instruments.

Instrument Connectivity Types

The IEEE P1687 hardware proposal defines two instrument-to-instrument connectivity types, Flat and Hierarchical. The Flat connectivity scheme has four sub-types: Flat, Daisy-chain, Star and Concatenate. Flat connectivity implies a direct connection between the 1149.1 TAP controller and a first-level instrument in the P1687 Zone or between the 1687 Gateway and an element at the end of a hierarchical structure (Figure 2). In this kind of structure, only one embedded instrument can be addressed at a time by the TAP controller’s TDI-TDO scan path.

Another flat type of connectivity, the Star configuration (Figure 3), avoids some of the tradeoffs inherent in Flat and Daisy-Chained schemes. With a star configuration, multiple instruments are placed in groups so that more than one instrument can be controlled at a time.

In a P1687 hierarchical connection scheme, the control mechanisms for an embedded instrument are contained in that instrument’s instruction register. The description of hierarchical constructs refers to a source instrument as a “parent” and a target instrument(s) as a “child.” Three types of parent-instrument/child-instrument hierarchical schemes are described: Replace-Parent, Concatenate-Before-Parent and Concatenate-After-Parent. With these latter two types, the TDI-TDO connection that is passed on to the child sources TDI and receives TDO at the point described.

A full description of all of the proposed connectivity schemes can be found in the hardware proposal document.

IJTAG at the Board Level

At least part of the motivation behind the IJTAG initiative is to allow access to embedded instruments so they can be used over and over again and in different environments besides wafer test or ATE test. P1687 embedded instruments could also be used to access traditional instruments during system integration to perform hardware chip debug or chip-yield analysis. Figure 4 below shows a board-level architecture, illustrating how an IJTAG device would be linked and interact with three JTAG devices. In this instance, placing the JTAG devices in bypass mode would enable fast access via the 1149.1 TAP to the instruments embedded in the P1687 device.

Next Steps for IJTAG

While the hardware proposal document is being reviewed, the IEEE P1687 working group has now turned its attention to other issues, including the definition of description and protocol languages to describe features and attributes throughout the IJTAG architecture. Candidates for these languages are extensions to BSDL for the 1149.1 Overlap Zone and HSDL (Hierarchical Scan Description Language) for the P1687 Zone. In addition, the working group is examining an application programming interface (API) that would simplify the ability to use and reuse IJTAG embedded instruments that are accessed by 1149.1.

The IEEE P1687 working group has scheduled a meeting at the next International Test Conference (ITC), which will take place in Santa Clara, Calif., Oct. 23-27, 2007. For more information on this meeting, click here.