Embedded instrumentation and boundary scan
“People are trying some new and very interesting things when it comes to testing chips and interfaces,” said Steven Terry, ASSET’s Development Manager for Design Validation. “As the links between chips on a circuit board have gotten faster and faster, and as the chips themselves have gotten more and more complex in recent years, we’ve seen that the industry needs new test methodologies to cope with this situation.”
 In relation to faster links and more complex chips, much of what Terry and others at ASSET are investigating and developing falls into a bucket that’s been labeled “design validation.” Of course, there are test methodologies in this bucket too, and certainly a few debugging techniques to boot. But what distinguishes design validation from traditional boundary-scan test and debug is the presence of embedded validation and validation functionality. Some would call this functionality embedded instrumentation.
“What we’re seeing in a lot of designs these days is that sending a data pattern at the boundary-scan rate across a static connection between chips is not testing all that needs to be tested,” Terry said. “Sure, we’ll find out whether there are shorts or opens, but there are other important aspects of the link that we may want to analyze. It may be a speed-related issue, an electrical issue or something else. To test for these kinds of issues, the engineer might want to use techniques like bit error rate testing (BERT) or inserting at-speed pseudo random data patterns across the link to see if the link is functioning properly.”
To test these various aspects of the system and to use the testing techniques that are needed, many organizations are opting to embed certain test functionalities at the chip level.
“More and more people are discovering how valuable it can be to include different kinds of test-related logic in ASICs,” Terry said. “That might mean embedding an engine for built-in self test (BIST) of logic, memory BIST or a complete logic analyzer. These elements, or embedded instruments, may work inside the chip or across on-board chip-to-chip links. We would refer to these sorts of activities as design validation.”
Terry pointed out that several design validation initiatives are already underway in the industry. Intel®, for example, has embedded its Interconnect Built In Self Test (IBIST) technology into its next-generation chipsets. (For more information on ASSET’s Intel IBIST technology, click here.) In addition, an IEEE working group has formed to investigate the development of a standard for accessing, communicating with and controlling instruments embedded at the chip level. This later effort has been designated the IEEE P1687 working group. It is also referred to as the Internal JTAG (IJTAG) working group. (For a related article on the IJTAG work group’s proposed hardware architecture, click here.)
Chip tools suppliers are also jumping on the embedded instrumentation bandwagon.  For example, Synopsys, the EDA system supplier, has introduced what it calls “a built-in test solution” for its PCI Express, Serial ATA and XAUI physical layer (PHY) interface products, which consists of an embedded instrument accessible only through JTAG. (For an online webinar from Synopsys on this technology, click here.
Still, the leap from embedded instruments to an effective design validation system or toolkit is sizable. Terry believes that boundary scan can bridge that gap.
“I look at boundary scan as the bridge for accessing and managing what’s inside the chips,” Terry said. “Ever since it was developed, boundary scan has been a bridge, for interconnect test, for FPGA programming, for memory test, for all sorts of things that have been embedded into chips. Boundary scan does this very well. It’s a great bridge.”
What boundary scan brings to these various embedded design validation techniques is a very well established, easy-to-use, well understood way of accessing, controlling and managing chip-level and board-level constructs. And, in boundary-scan systems like ScanWorks, it’s all wrapped up and displayed in an intuitive graphical user interface.
“When you come right down to it, embedded instruments have to be controlled by a set of registers. You may have a register to start an instrument, to count clocks, to store data or to perform other functions,” Terry explained. “There’s no better way to get to those registers and control them than through boundary scan.”
If events like the emergence of IBIST and the formation of the IJTAG working group are any indication, it would seem that the design validation “bucket” is filling up very quickly. |
