Connect - ASSET InterTech

New labs tap into needs
for board-level DFT
By Glenn Woppman
President and CEO
ASSET InterTech

I’d like to say we are very prescient, but that would be stretching the truth a bit. When we opened our first two DFT (design-for-test) Labs in San Jose and London, we thought we were addressing a need in the marketplace, but you never know for sure. What tipped the scales for us was when we asked ourselves: what would the leader in boundaryscan/JTAG do? That clarified everything.

Fortunately for us, we were right about the need for thorough and thoughtful DFT analysis. We just underestimated how great that need was. The immediate response to our DFT Labs has been remarkable. It appears that we’re filling a void in the marketplace.

The analyses that our DFT Labs perform are much more than the simple test coverage reports which some tools generate. For one thing, our analyses include design recommendations based on our more than a decade and a half of firsthand experience. We’ve seen just about every mistake ever made and we’ve also seen lots of examples of good JTAG design. One reason why we felt so confident about taking the plunge and opening our new DFT Labs was the fact that we had institutionalized and productized the collective DFT knowledge of ASSET and deposited it in our DFT Analyzer tool. Armed with DFT Analyzer, we knew our DFT Labs would do an outstanding job.

The initial acceptance of DFT Analyzer by the marketplace has also been encouraging. As a result, we’ve accelerated our plans for enhancing this exciting new tool.

As its name might imply, the Design-for-Test Analyzer is drawing the test and design functions closer together. That doesn’t mean that DFT Analyzer is a tool dedicated to the Design Department, although designers can and are certainly using it. DFT Analyzer is bringing the design and test functions closer together because it is something of a common ground that both can share. DFT Analyzer has the qualities of both a design tool and a test tool. And, more importantly, it simplifies the jobs of both designers, who have a great deal on their minds outside of test, and test engineers, who can do only so much when fundamental testability characteristics are missing from a design. Ultimately, the organization wins because new products are brought to market faster.

Because DFT Analyzer is useful to both designers and test engineers, it makes one wonder where exactly in the organization is it being used? Certainly it has been deployed in test and design departments, but it’s also been implemented by groups that bridge the gap between these two.

Verification engineering groups, who are charged with validating whether a design is ready to move into

manufacturing, are also taking advantage of DFT Analyzer toquickly and efficiently determine the testability of a design before prototypes are built. In fact, because one of the outputs of DFT Analyzer is a set of recommendations for testability improvements to a design, it adds value to the verification engineering function. Instead of issuing an overly simplistic “pass/fail” on a design’s testability characteristics, DFT Analyzer gives verification engineers the ability to recommend specific changes that will rectify JTAG test deficiencies.

Quantifying DFT Benefits

The complexity of an ROI calculation can be daunting at times, so we’ve simplified the process for you with an automatic ROI worksheet on our web site. Just fill in the blanks and the logic

embedded in the worksheet calculates the cost savings DFT Analyzer will generate for your organization. Click the icon to view the DFT Analyzer ROI worksheet.

DFT: A big payoff

I hope you can see that ASSET has put a lot of time and effort into DFT. Why have we invested so much in DFT when they are many aspects of JTAG technology that demand our attention and resources? We believe – no, we know – that the better the testability in your design, the better off you and your organization will be. The payoff for high-quality DFT is huge.