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DFT Analyzer named DesignVision finalist
for 2007
Recognizing that ASSET’s design-for-test tool, DFT Analyzer, offers innovative assistance to PCB design and test engineers, the International Engineering Consortium (IEC) made DFT Analyzer a finalist in its 2007 DesignVision Award program.
“Our DesignVision Awards honor those catalyzing positive change in high-technology, business, and academia, completely in line with the IEC’s mission,” said IEC President John Janowiak. “We are delighted to recognize our DesignVision Finalists and share the best design advancements and innovations with the entire industry.”
ASSET’s DFT Analyzer was one of three finalists in the printed circuit board (PCB) design tool category. Entries in the DesignVision program were  judged on the basis of their innovation, uniqueness, market impact, customer benefits and value to society.
“To capitalize effectively on the many benefits of boundary scan technology, JTAG should be a consideration during the design of circuit boards and chips,” said Alan Sguigna, vice president of sales and marketing for ASSET. “This is becoming even more critical these days because additional technologies, like IEEE 1149.6 for testing high-speed AC-coupled buses and Intel® IBIST (Interconnect Built In Self Test), depend upon the JTAG infrastructure to perform their functions. The better boundary scan is designed into boards and chips, the greater the benefit that manufacturers derive from it, beginning with prototype debug in design and following a product through to manufacturing and support.”
For more information on ASSET’s DFT Analyzer, click here.
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