Connect - ASSET InterTech

Where does boundary scan fit?
Part 2
By Alan Sguigna
Vice President of Sales and Marketing
ASSET InterTech, Inc.

In part 1 in this series of articles, I described how JTAG test fits into a product’s overall test methodology. Most test methodologies encompass both structural (assembly) and functional (system) test.

JTAG testing, as I pointed out in part 1, plays a powerful role within the context of the PCOLA-SOQ test methodology. Overall, boundary scan is well-suited to circuit boards with high digital content. In addition, it is a very cost-effective test technology. In some designs JTAG can be used to approach 100 percent test coverage for the “P”, “O”, “S” and the second “O” in the PCOLA-SOQ methodology.

“P”, which stands for presence, would represent a test that validates whether a device is present at a certain location on a printed circuit board (PCB). The first “O” signifies orientation or whether a device is correctly oriented on the PCB. “S” indicates shorts and the second “O” stands for opens; JTAG thoroughly tests for both shorts and opens.

Boundary scan can also provide partial coverage for the “C” or whether the correct device is present and “L”, whether the device is live. When the attributes of PCOLA-SOQ that have partial or no coverage from JTAG are covered adequately during functional test, then JTAG testing can be an excellent structural test solution on its own. The combination of JTAG structural test and functional test will yield close to complete test coverage. Alternatively, boundary scan can be used in conjunction with other structural test technologies to approach 100 percent coverage on structural test.

At this point, it is worthwhile noting some of the many benefits of boundary scan:

What Boundary Scan Does Well

Now, let’s look at the return on investment (ROI) for JTAG testing when it is used in conjunction with other common structural test technologies and when it is used as a standalone test technology.

JTAG with Flying Probe Testers (FPT)

Recently, an equipment manufacturer approached ASSET with a test problem. This particular OEM was producing a low-volume, high-cost, highly complex design. Without the cost of test, the fully burdened cost of this PCB was $2,000. The board would not be produced in high volume, so the OEM had elected to perform assembly test with a Flying Probe Tester (FPT). The cost of creating a fixture for In-Circuit Testing (ICT) would be prohibitive because of the low production volumes.

Unfortunately, the manufacturer encountered assembly test problems. Specifically, the time required to perform FPT tests on each board – a full two hours – was excessive. In addition to the time-related cost of FPT testing, there were costs associated with developing FPT tests. In the end, the manufacturer estimated that the total cost of FPT testing added another $200 or 10 percent to the total cost of each PCB. You can imagine that the company’s marketing department was screaming at the engineering and manufacturing departments to find ways to lower the overall cost of the design and drive up the gross margins on the product.

This OEM came to realize that it could substantially lower its overall cost-of-test by supplementing FPT test with boundary scan test. Digital nets on the PCB would be tested by boundary scan while FPT tested the analog portions of the board. The results were astounding. The cost of testing each board shrank by 75 percent. Moreover, the fully burdened cost of producing the board shrank from $2,200 to $2,050, Needless to say, the test engineer who pioneered the strategy was a hero.

JTAG with In-Circuit Testers (ICT)

The complementary nature of boundary-scan test can be used to great advantage where ICT is an integral part of the overall test strategy. Depending upon the needs of the manufacturer and the particular design being assembled, JTAG test can be highly integrated or loosely coupled to the ICT test systems in a production line. In any case, the cost savings that are derived from supplementing ICT with boundary-scan test are significant.

For example, Lucent Technologies (now Alcatel-Lucent) found that it could save close to a million dollars a year by integrating ASSET’s ScanWorks boundary-scan testing into its Agilent 3070 ICT systems. Cost savings were generated from the following factors:

Because of the automatic test pattern generation (ATPG) of ScanWorks as well as its many other test development tools, boundary-scan tests can be developed in a fraction of the time it took Lucent to design and develop ICT fixtures and tests. Replacing ICT test coverage with boundary scan test coverage reduced development time for ICT test fixtures significantly. Moreover, Lucent was able to re-use many existing ScanWorks tests, further reducing test development time without sacrificing test coverage.

When the number of test probes on an ICT test fixture is reduced, the cost of the fixture drops dramatically. By implementing ScanWorks’ JTAG tests, Lucent reduced the complexity of its ICT fixtures, accelerated the development of ICT fixtures and reduced their costs. ScanWorks actually features an automatic Test Point Reduction Report which analyzes a design and determines where boundary-scan test coverage can replace ICT test coverage and thereby eliminate ICT test points on the PCB. To review a recent Connect article on the Test Point Reduction Report, click here.

By eliminating approximately 50 percent of the test probes from its ICT test fixtures, Lucent substantially reduced its

Lucent demonstrates how ScanWorks for the Agilent 3070 can save nearly $1 million per year

fixture maintenance costs as well as the cost of replacing probes.

To review the complete case study on Lucent’s million-dollar savings from integrating ScanWorks into its 3070 ICT systems, click here.

A recent Connect article entitled “Flexible configurations accelerate integration of ScanWorks with ICT systems” explained the ease with which ScanWorks can be integrated into ICT systems from suppliers like Agilent, Teradyne (GenRad) and others. To review this article, click here.

For more information specific to ScanWorks’ integration options with Agilent’s ICT systems, click here.

When JTAG is used as the primary or exclusive means of assembly test, testing costs can drop through the floor.

Beginning with the prototype stage of design, using JTAG exclusively has enormous benefits. At this point, it’s usually too early and too costly to create an ICT fixture because the design is still churning. And in most cases the cost and effort of outsourcing FPT test on an early design is prohibitive. In the end, most manufacturers realize that placing the test methodology for prototypes on the critical path for delivering a product unnecessarily jeopardizes the product’s production schedule.

I once encountered a rather dramatic example of this situation. The telecom tester company where I worked was in a race to develop and deliver to market the industry’s first OC-192 line-rate router tester. A large telecom OEM was prepared to award a sizable order to the first supplier that could provide such a tester in quantity. At that time, OC-192 transceivers were in extremely short supply from the component vendors; the transceivers cost $12,000 each and the tester boards were priced at $150,000 and up. Needless to say, faced with the opportunity of selling 50 of these PCBs was a strong motivator to be the first-to-market. The pressure to perform was intense.

One idea we brainstormed was to use boundary scan for the early prototype testing instead of the usual flying probe testers. Every day counted and the two or three days for creating and testing the boards on FPT systems were on the critical path. By using JTAG we were able to crank out prototype tests quickly and do it in-house. This turned out to be even more critical since we ended up re-spinning the board three times. Each time the design changed, regenerating the boundary scan tests was only a matter of hours instead of days. In the end we were first-to-market with the OC-192 tester and the telecom OEM was thrilled to be able to test its routers before shipping them. But then the telecom meltdown hit and the manufacturer never ordered the 50 blades; but that’s a story for another day.

Boundary Scan Fits!

I hope the two articles in this series have shown how the rapid ROI on boundary scan technology can make it a good fit in just about any test strategy during design for prototype debug and manufacturing for structural test and in-system programming. And, when JTAG teams up with ICT, FPT or other test technologies, it improves the cost effectiveness of all of the technologies involved by lowering the overall cost-of-test.