Connect - ASSET InterTech

The response of the marketplace to the recent opening of two DFT Labs – one in San Jose and the other outside of London – has validated what we thought was true: there is a very real need for thorough and thoughtful design-for-test analysis before prototypes are built. Of course, it helps that we have our DFT Analyzer to perform the analysis and make design recommendations.

INSIDE ASSET

Standards development benefits entire industry

In a recent guest commentary in an e-newsletter distributed by Test & Measurement World magazine, ASSET’s president and CEO Glenn Woppman explained how the investment of time and effort on the part of companies in the boundary-scan business has paid off handsomely for the entire industry.

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ScanWorks’ External I/O Management
increases test coverage

The elusive quest for 100 percent test coverage has led to a new ScanWorks feature called External I/O Management. With this new feature, users of ScanWorks 3.8 will find it easier and simpler to extend JTAG test coverage to signals that are routed off the board to a connector.

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DFT Analyzer named one of three finalists in prestigious DesignVision Awards

For a number of years the DesignVision Award program by the International Engineering Consortium (IEC) has effectively recognized some of the leading-edge electronic design tools. When the 2007 finalists were announced just after the first of the year, ASSET’s DFT Analyzer was one of the three tools named in the printed circuit board (PCB) design category.

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New Boundary Scan Tutorial features expanded content

In the new printing of ASSET’s popular Boundary Scan Tutorial, the content has been expanded to include new chapters on recent JTAG developments such as the IEEE 1149.6 Boundary-Scan Standard for Advanced Digital Networks, new design-for-test guidelines and much, much more. Learn more and request your free copy today.

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New video explores ASSET’s role in the emergence of boundary scan

A new video produced by ASSET looks at the contributions the company has made to the evolution of boundary scan technology in recent years. The video points out the many achievements and the industry recognition that ASSET has received. In addition, several new advancements such as IJTAG and System-level JTAG are mentioned in the video. If you’d like to take a sneak peak at the video, click on the icon below or….

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Survey shows best-in-class user
satisfaction for ScanWorks

The recently completed ASSET User Survey showed that overall user satisfaction is on the rise, increasing by more than 10 percent from last year’s survey. At the same time, the results of the survey will help ASSET plot its product development course as well as how it will deploy corporate resources.

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Discover the rewards of Scan Path Discovery

Some tedious tasks are best avoided and laboring for hours or days over schematics that could stretch into hundreds of pages is one of them. That’s what engineers sometimes face when they’re given a circuit board design they’ve never seen before and they are told to compile a ScanWorks design description of the scan path so tests can be developed. This is where Scan Path Discovery comes in and rescues that beleaguered engineer so he can quickly move on to more useful and fulfilling tasks.

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Boundary scan emerges as a prime test and validation method for high-speed serial buses

Testing shorts and opens with boundary-scan technology is one thing, but applying the JTAG infrastructure to validate designs with high-speed serial I/O (HSSIO) buses like PCI Express, Serial RapidIO and others that have speeds in the five to 10 gigabits per second (Gbps) range is quite another. But that’s precisely what’s happening and for good reason. In a new twist, these blindingly fast buses could boost boundary scan’s deployment in traditional functional test roles.

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