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Fitting in by standing out: A closer look at assembly test
By Alan Sguigna
Vice President of Sales and Marketing
ASSET InterTech, Inc.

JTAG testing and in-system programming techniques are finding their way into more and more applications these days. For example, Microsoft has adopted boundary scan for testing its next-generation Xbox 360 video game console and Delphi has deployed it to test its automotive systems.

The forces driving this expanding adoption rate are not new. In fact, the same qualities could be attributed to just about any successful technology. First, JTAG has capabilities and functionality not found in any other test technology. In other words, it gives test engineers the ability to approach 100 percent test coverage. Second, it does what it does at a great price/performance ratio. Performance capabilities are certainly every technology’s raison d’etre, but cost/performance carries the day in the marketplace.

Based on these criteria, JTAG test and in-system programming are fitting in rather well.

Fitting In by Standing Out

At the board and system level, test engineers face numerous choices when defining a test strategy for a particular product. Certainly many different test technologies and methodologies vie for attention, all promising to be a panacea and meet many, if not all, of an engineer’s test requirements. Options range from oscilloscopes to logic analyzers, protocol analyzers, manufacturing defect analyzers (MDA), bit blasters, in-circuit testers (ICT), automated X-ray inspection (AXI), flying probe testers (FPT), automated optical inspection (AOI), signal generators, protocol emulators, JTAG-based emulators and so on.

In addition, practically all products require some sort of “home-grown” functional test procedures that validate the unique characteristics of the system. No single off-the-shelf test system is capable of meeting these functional test requirements. Trying to devise a test strategy that takes advantage of the best capabilities of the best test technologies can be a daunting task. The welter of alternative technologies and methodologies is certainly formidable.

Frequently, the best way to build an effective test strategy is to de-construct the problem. Divide the task into smaller, more manageable pieces. Most companies break their test strategy into two basic parts:

These two segments of test can be elaborated as follows:

Table 1: Assembly Test and Functional Test

The table above illustrates that a successful test strategy incorporates both assembly and functional test. Assembly test without functional test could result in circuit boards or assemblies that have been manufactured flawlessly, but they don’t work. And functional test without assembly test might result in lower manufacturing yields, as the “bone piles” of non-functional printed circuit boards (PCB) grow because technicians have no way of diagnosing all of the problems.

Another issue to consider is the portability of test methods. A test technology that is portable to the point where it can be deployed early in the development phase to wring out prototypes and then accompany the system as it migrates to pre-production and volume manufacturing will generate cost savings from economies-of-scale and test re-use. Moreover, the body of knowledge compiled on the system as it moves through the various stages of its product life will facilitate efficient root-cause analysis that can quickly identify and solve design and manufacturing flaws.

The critical importance of assembly test has been established to the point where it has been embraced by the vast majority of electronics manufacturers. An assembly test strategy can be accomplished quickly and it doesn’t have to be very expensive. There is a wide selection of test technologies to choose from, including ICT, MDA, FPT, AXI, AOI, JTAG and others.

The name of the game in assembly test is coverage. The Holy Grail of assembly test is to eliminate the possibility of any manufacturing defect prior to functional test. Test engineers strive for 100 percent test coverage for all possible manufacturing defects. The challenge is to define what 100 percent coverage means, recognizing that although this is the goal, it probably is not generally attainable under real-world conditions. There are always trade-offs among various factors, including test coverage, the cost of test and the time it takes to develop, deploy and apply tests. In all likelihood, reaching 100 percent assembly test coverage would take a plethora of test technology and various tools, require a great deal of time on the assembly line and cost a bundle in terms of test equipment and technician time.

To better understand the assembly test process, a number of models have been suggested. The most prevalent of these is known as the PCOLA-SOQ model, which stands for:

Presence (the device is present)
Correctness (it is the correct device)
Orientation (if polarized, the device is not reversed or rotated by 90 degrees)
Live (at a very basic level, the device is functional, although this does not imply a full functional qualification)
Alignment (the device is centered, free of skews or small rotations)

Shorts (unwanted continuity to other connection points nearby)
Opens (discontinuity between the PCB and a device’s connection points)
Quality (the device and PCB are free of malformations, excess or inadequate solder, cold solder voids and other quality problems)

PCOLA refers to device test coverage; whereas SOQ refers to connection (interconnect) test coverage.

Table 2: The PCOLA-SOQ model for assembly test

It is important to note that the PCOLA-SOQ model refers only to the assembly characteristics of the PCB, not the logical functionality of the devices on the circuit board or the circuit board itself. This introduces some nuances that a test engineer must be aware of. In particular, under the device test category, the “Live” attribute means only that the device is not dead in the sense that it can be powered up; it does not refer to any of the operational or performance characteristics of the device. These are validated during functional test.

Similarly, the “Correctness” attribute can be difficult to ascertain. For example, a test of a resistor may indicate that the right resistor value is present, but it may not reveal whether a carbon composition resistor or a wire-wound device is present. In these types of cases, there will be only partial test coverage under the PCOLA-SOQ model instead of full coverage or no coverage at all.

Comparing the maximum theoretical PCOLA-SOQ test coverage for various test technologies is useful. See the table below.

Table 3: PCOLA-SOQ test coverage for various
test technologies

The values listed in Table 3 are maximums for theoretical achievable coverages. A rigorous design-for-test analysis would probably include one or several test technologies, such as JTAG, ICT, AOI or FPT, and the strategy would take into account the specifics of the design being tested. In the end, each of the criteria in the PCOLA-SOQ model would probably be assigned a weight on a scale reflecting the critical nature of each characteristic in the overall test strategy.

Since no one test technology by itself can guarantee 100 percent test coverage, many manufacturers combine several technologies to achieve as much coverage as possible. Of course, there will always be trade-offs among time, cost and coverage. Untimately, test engineers must analyze each case on its own and often make a judgment call on which test technologies to include in the test strategy.

Fitting JTAG into PCOLA-SOQ

Even though boundary scan as a test method shines in connection tests (shorts, opens and quality) in the PCOLA-SOQ model, it can be applied to test device characteristics as well.

To test for the presence (P) of a device, boundary scan can examine a circuit board and verify that all of the boundary-scan devices that have been specified in the design database are present. The presence of non-boundary scan devices can be verified too if models of these devices have been included in the design database.

For correctness (C), JTAG test tools can read a boundary-scan device’s IDCODE register and compare it against the contents of the device’s Boundary Scan Description Language (BSDL) file to ensure that the right device has been implemented. For non-boundary scan cluster models, a JTAG test tool will flag the condition when it reads vectors on a receive scan cell that do not match what is expected.

Verifying the orientation (O) of a device means checking whether devices are rotated by 90 degrees or more. JTAG test tools can ensure 100 percent test coverage for the orientation of boundary-scan devices since they simply will not function properly if they are not orientated properly.

To test whether a device is live (L), boundary scan is capable of partial test coverage since it can only verify the boundary-scan functionality of the device and not its overall functionality. Practically speaking, only functional test can verify the all of the functionality of a device.

Alignment (A) refers to rotations of a device that are less than 90 degrees, including “billboarding or tombstoning” where the device is soldered in place but it is positioned on its side rather than flush with the board. If the device is correctly soldered to the circuit board, JTAG can not test for these conditions because there may be no faults in the electrical connectivity of the device. These conditions may be symptomatic of a process problem or they may be precursors to reliability problems in the future. No electrical test can detect these flaws, but AOI systems, for example, may be able to read the markings on a device with sufficient accuracy to detect slight changes in alignment.

Shorts (S) on boundary scan devices and modeled non-boundary scan devices are readily detected by JTAG systems. In fact, even with its limitations (See Table 4 below.), boundary scan is equal to or better than other test technologies when it comes to detecting shorts. JTAG tests for shorts between all nets accessible with boundary scan while ICT only tests for shorts between nets on adjacent pins and traces.

For opens (O), JTAG really shines. Since it is a vector-based digital technology which originates “behind the pins”, so to speak, boundary scan offers test coverage for hard-to-reach opens, such as those on the underside of a ball grid array (BGA) package, on hidden and blind vias, on device pins that are covered by heat sinks or shields, and on other places on a PCB where an ICT or FPT system can not reach. Some ICT vendors have deployed non-vector-based technologies to address this issue. For example, Agilent’s TestJet® runs on 3070 and i5000 ICT systems. To find opens, it measures the capacitance between each device pin and a metal shield that has been placed over the device. Of course, if the shield can not come into contact with the device or if the device does not support the associated logic, TestJet will not work. Spea’s FPT ElectroScan offers another example of this, but this test adds substantially more time to the test process.

The quality (Q) metric makes qualitative judgments on solder joints, such as the presence of excess solder, insufficient solder, poor wetting or voids. Again, these conditions may indicate flaws in the fabrication process which could create reliability problems in the future. Practically speaking, only AXI can offer full coverage for these problems.

Standalone or Complementary

In summation, the cost-effectiveness and relatively low cost of entry for boundary-scan test technology has earned it a place across many industries and in many applications. With circuit boards that have a high digital content, boundary scan is an excellent standalone assembly test technology because it provides very high test coverage on its own. At the same time, JTAG can be easily implemented in a complementary relationship to other test technologies if they are needed to achieve the level of test coverage being sought.