 New embedded techniques on the horizon for validating and testing designs with high-speed buses
By Tim Caffee
Vice President of Design Validation
ASSET InterTech, Inc.
Manufacturers of electronic systems with very high-speed interconnects between chips are increasingly exploring alternative techniques in design validation and production because current test techniques break down.
The traditional method in design validation of probing with an oscilloscope to determine the integrity of signals on buses is not effective when bus speeds get in the neighborhood of five to six giga-transfers per second (GT/s). For example, the location of a probe and capacitance can create problems with oscilloscope measurements. The effects of a flaw or design defect on system performance may not manifest itself until later after the system has been manufactured in high volume and it has been rolled out and installed in customer location.
To make up for this deficiency, new software-based signal analysis technology is being embedded by some equipment and semiconductor manufacturers, giving board designers the information they need to detect design flaws. Unlike traditional boundary-scan tests that pinpoint structural faults like opens or shorts, these new embedded procedures use margining to determine where flaws in the design might jeopardize the optimum performance or eventually cause a failure on the circuit board.
Similar to manually analyzing eye diagrams on oscilloscopes, this embedded technology generates “virtual” eye diagrams that identify where AC defects are present. Problems like crosstalk, inter-symbol interference and other sources of electrical noise on high-speed buses can degrade the performance of the system. Identifying flaws early in the process gives the manufacturer time to correct the design before it moves into high-volume production. Various methods, including boundary-scan’s four-wire interface (or JTAG), can be employed to access the embedded validation and test structures.
Automating Design Validation
Although design validation is not new, embedding the tools that are needed to perform it and automating the entire process are. Even if the old manual methods were still feasible at high bus speeds, automated validation processes are needed to accelerate the entire design process and bring new high-speed products to market much faster.
Validating a design with manual measurements could take a design engineer a month to complete. With embedded validation structures and virtual signal integrity analysis, design validation can be reduced to less than a day because the entire circuit board is stimulated at one fell swoop, quickly identifying any design defects that may be present.
In addition, the thoroughness of embedded design validation technology is vastly superior to traditional oscilloscope-based testing since the embedded test can produce more stress on the system. When a design is manually validated by an engineer probing the circuit board’s buses, test patterns are placed on only one bus at a time and the results are observed on the oscilloscope. Embedded validation methods are able to stimulate all buses across all ports and channels at the same time. Automatic analysis of marginal performance then flags defects like crosstalk generated by neighboring traces that are too close to each other. By stimulating the entire design, interrelated flaws that are dependent on one another can be identified.
Just Scratching the Surface
More work certainly needs to be done on developing standardized embedded design validation technology. The benefits in terms of shortening time-to-market and reducing the risk of poorly performing designs has attracted the attention of major chip and equipment manufacturers in the industry. This in itself will hasten the development of this exciting new technology.
For more information on design validation, click here.
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