ASSET raises the bar with new innovations in JTAG
 

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DFTA page with DFT horror story

"Manufacturing" page with ATE info

BSDL Horror story


 

New Articles Published

Evaluation Engineering article: Expanded Role for JTAG DFT"

Test & Measurement World article coming in next issue!


 

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OBSERVATIONS

More than just a pretty face…
by Glenn Woppman

Sure, colorful graphics will catch your eye. And animated characters may capture your attention momentarily. But ease-of-use is a whole lot more than just the pretty face that a system puts on your computer monitor. Ease-of-use or, more precisely, usability goes well beyond superficial appearances. In fact, it’s a lot like Microsoft when it talks about its software being “People Ready.” Only we call it usability. With ScanWorks and DFT Analyzer, we’re out to raise the usability of JTAG to an entirely new level.

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Have you ever seen one of the educational videos that makes ScanWorks so “usable?” Click here to see one now.

 

TEST DATA OUT

Embedded test structures are critical to validating and testing designs with high-speed buses.
by Tim Caffee

Bus speeds on new designs continue to climb higher and higher. After a certain point, traditional design validation techniques break down because of the high speeds of the buses. New techniques based on embedded software structures and signal integrity analysis are being investigated as possible solutions.

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INSIDE ASSET

Where does JTAG fit?
by Alan Sguigna

As boundary scan test technology proliferates into video game consoles, automotive systems and an ever widening spectrum of systems, a couple of basic questions emerge: Where and how does JTAG fit in? Where does it fit into the scheme of an overall test strategy for a particular product and how does it fit in among all of the other alternative test technologies that are available today? The answers aren’t simple, of course, but here are a couple of clues: think test coverage and cost-effectiveness.

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Part 1 of 2. Next issue:
Where does boundary scan fit into functional/system test.

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ASSET presents one paper, co-authors another at ITC

Intel®’s Interconnect Built In Self Test (IBIST) technology involves test structures embedded at the chip-level which can be accessed by ScanWorks. At the upcoming ITC, a paper by ASSET’s Senior Application Engineer, Eric Johnson, will present the results of an experiment which put IBIST through its paces. In addition, Adam Ley, Chief Technologist, has co-authored a paper on a descriptive language for analog boundary scan. And lastly, Dave Bonnett, Technical Marketing Manager, will discuss JTAG design for test analysis during a corporate presentation session.

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IJTAG standard making progress – Demo scheduled for International Test Conference
by Ken Posse

The committee defining the Internal JTAG (IJTAG) draft standard (IEEE P1687) has been hard at work for more than 19 months and now the fruits of the group’s labor are becoming apparent. A demonstration of IJTAG’s on-chip access and control technology for testing and design validation is scheduled for the ASSET booth (Number 502) at the International Test Conference, Oct. 24-26 in Santa Clara, Calif. Come by and check it out.

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Remote embedded system JTAG demonstrated at ITC

It may sound futuristic, but applying JTAG tests on an entire system located miles away from a ScanWorks system will be demonstrated in the ASSET booth at the International Test Conference, Oct. 24-26, in Santa Clara, Calif. Firecron Ltd. of the UK and ASSET have teamed up to embed a JTAG controller in a system and apply tests remotely over an Internet link.

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New ScanWorks controller combines boundary-scan and functional emulation testing

A new ScanWorks PCI controller card, the PCI-200EJ, is the first to be able to perform both boundary-scan and microprocessor-based functional emulation testing. ScanWorks has supported emulation testing with its ScanWorks Extended JTAG Coverage product, but two controller cards were needed, one for JTAG and the second for emulation testing. Now, the PCI-200EJ does both.

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BSDL validation accelerates introduction of “dot-6” devices

Whenever a new standard enters the scene, there’s a ramp-up period. It takes time to get it right. The IEEE 1149.6 Boundary-Scan Standard for Advanced Digital Networks was finalized two years ago and the number of semiconductor devices to incorporate it is growing daily. The accuracy of these devices’ Boundary Scan Description Language (BSDL) files is crucial for an effective entry to the marketplace. ASSET’s BSDL validation service is smoothing out some of the bumps along the way.

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ASSET opens Boundary Scan
Technology Center in Malaysia

Many of the electronic manufacturing services (EMS) firms with plants in Southeast Asia are realizing the value of boundary-scan technology. Spurred on by their customers who want to implement the most efficient test and in-system programming strategies possible, EMSs are rapidly implementing boundary scan. As a result, ASSET has announced it is opening a Boundary-Scan Technology Center in Penang, Malaysia.

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New features enhance openness of ScanWorks

ScanWorks is all about JTAG test coverage. The more, the better. As a result, the latest version of ScanWorks (3.8) has several new enhancements which open it up to third-party products and technologies from other companies. Users benefit with increased test coverage and added functionality.

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