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Testing the test technology for high-speed buses
An ASSET-authored technical paper presented at the
upcoming International Test Conference (ITC) in
Santa Clara, Calif., Oct. 24-26, is a case study
involving the 2.5 Gbps PCI Express (PCIe) bus, the Fully Buffered DIMM (FBD) channel, and the new Intel® Interconnect Built In Self Test (IBIST) technology. In this study, the embedded IBIST test structures are accessed by boundary scan and ScanWorks.
ScanWorks and its Intel IBIST capabilities performed the experiments by applying special JTAG instructions to set up the tests, start them, determine when they complete and read back failure information. The actual pattern generation and error checking was done by the Intel IBIST test structures that were embedded in the chips. The experiment investigated the impact on fault detection and diagnostics when normal operations, such as the routine link training conducted by PCIe, is not possible because of structural faults.
The system on which the experiments were run had seven testable PCIe buses with four lanes each and four FBD channels. After structural faults were introduced, test patterns were applied across the buses. Data was gathered on how the system’s embedded IBIST test and diagnostic capabilities were affected when normal operations were impaired by structural faults to the circuit board.
ScanWorks created, edited and controlled the tests that were applied to the high-speed buses in the system that formed the basis of the case study. To create test sequences for the unit under test, the circuit board’s netlist information and BSDL files, including IBIST extensions, were imported into ScanWorks. With this information, distinct tests were created for several configurations of the PCIe and FBD buses.
A number of different types of faults and tests were used in the experiment to simulate problems that might arise in a real-world manufacturing environment.
Eric Johnson’s paper will be presented at ICT at 8:30 a.m. on Wednesday, Oct. 25.
Although he will not present the paper, Adam Ley’s co-authored paper on an analog boundary scan description language will be presented at 2 p.m. on Tuesday, Oct. 24.
Dave Bonnett’s corporate presentation on JTAG Design for Test Analysis is schedule for 10:30 a.m. on Wednesday, Oct. 25.
For more information on ScanWorks for High-Speed Bus testing, click here.
For more information on ScanWorks for Intel IBIST,
click here.
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