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 IJTAG standard making strides
By Ken Posse
Chairman, IEEE P1687 Working Group
A group of interested parties met informally at the 2004 International Test Conference (ITC) to talk about internal on-chip control and access methods, as well as the absence of a standard for testing, characterizing and validating the performance of semiconductor devices. Since then, the group has been sanctioned by the IEEE and the standard it is working on is now known as the IEEE P1687 Draft Standard for Access and Control of Instrumentation Embedded Within a Semiconductor Device. The committee itself refers to its draft standard as the Internal JTAG (IJTAG) spec.
The progress that the IJTAG committee has achieved will be demonstrated in ASSET’s booth (No. 502) at the upcoming ITC, Oct. 24-26, in Santa Clara, Calif. The demo will explain the IJTAG architecture implemented in the unit-under-test (UUT) and then show how the IEEE 1149.1 boundary scan (JTAG) interface is used by IJTAG to access and control embedded instrumentation without affecting other on-chip logic.
What is IJTAG?
The IJTAG standardization effort has grown out of a realization that an industry-wide method for accessing and controlling internal test and other mechanisms that characterize the performance of semiconductor devices will accelerate and improve the efficiency of chip design and production.
The complexity of many chips today exceeds the capabilities of technologies that access and manipulate the internal functionality of semiconductor devices. For example, a system-on-a-chip (SOC) or an application specific integrated circuit (ASIC) device can be integrated with multiple processing cores, several different types of memory, logic elements, high-speed serial input/output functionality and much more. At the same time, chip fabrication geometries continue to shrink. Many of the most advanced SOCs and ASIC are moving from 90 to 45 nanometers and even smaller process nodes are on the horizon.
A number of methods such as embedded built-in-self-test (BIST) engines, SERDES (serializer/deserializer) manipulation techniques, bit error rate tests (BERT) and others are already being used to stimulate and measure the behavior of on-chip circuitry, but none of these methods are industry standards. In addition, characterizing internal functional blocks often involves observing the interaction among on-chip partitions and this means the use of synchronization and triggering techniques.
The IJTAG group has settled on the IEEE 1149.1 boundary-scan interface for its physical access to internal chip-level structures. Eventually, the committee hopes to define standard protocols for controlling the BIST engines, BERT test processes and other internal test methods, or “instruments” as they are called in the P1687 draft specification, that are in use today. This will involve defining a standard way of describing the architecture of an internal instrument or instruments so test equipment can automatically implement the proper access protocols. This description language could end up looking something like Boundary-Scan Description Language (BSDL). With this sort of standardized description language, any test system would be able to access and control any embedded instrument.
Recent IJTAG Developments
Most recently, the IJTAG Working Group has been examining whether the IJTAG physical interface under consideration, which is primarily the JTAG IEEE 1149.1 Test Access Port (TAP), is serviceable for accessing and controlling virtually any embedded test or instrumentation-related circuitry. The group has studied examples of embedded instruments such as IEEE 1500 wrappers, SERDES I/O control, embedded logic analyzers, embedded breakpoint control and others. The findings of this research is leading the group to the development of an intermediary P1687 “interface” situated between the IEEE 1149.1 JTAG TAP physical interface and the instrument being accessed and controlled. Specifying such an interface in the IJTAG standard simplifies other aspects of the standard, such as the architectural language, the procedural language and the High-speed Universal Block (HUB) port.
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