Testing and validating Gigabit
per second (Gbps) buses
As if it wasn’t tough enough testing Gbps buses, board layout constraints are denying physical access to some high-speed buses and making them even more difficult to test and validate. A technical paper to be presented by ASSET at the upcoming International Test Conference (ITC) in October in Santa Clara, Calif., explores a case involving the 2.5 Gbps PCI Express (PCIe) bus and Intel’s new Interconnect Built In Self Test (IBIST) test technology.
In this case study, the embedded IBIST test structures are accessed by boundary scan and ScanWorks. The paper recounts experiments involving Intel IBIST technology, the PCIe bus and the Fully Buffered DIMM (FBD) channel.
ScanWorks and its Intel IBIST capabilities were utilized in the experiments to apply special JTAG instructions to set up the tests, start them, determine when they complete and read back failure information. The actual pattern generation and error checking was done by the Intel IBIST capabilities embedded in the hardware. The experiment investigated the impact on fault detection and diagnostics when normal operations, such as the routine link training conducted by PCIe, is not possible because of structural faults on the PCB.
HP server hardware with both the PCIe and FBD buses formed the basis for the experimentation. The system contained seven testable PCIe buses with four lanes each and four FBD channels. Structural faults were injected into the system followed by test patterns that were applied across the buses. The experiment sought to determine how the system’s embedded testing and diagnostic capabilities would be affected when normal operations were impaired by the presence of the structural faults.
ScanWorks, running on a PC and connected to a JTAG controller via a USB cable, created, edited and controlled the tests that were applied to the high-speed buses in the HP server system. To create test sequences for the unit under test, the circuit board’s netlist information and BSDL files, including IBIST extensions, were imported into ScanWorks. With this information, separate tests were created for different configurations of the PCIe and FBD buses.
The intent of the test patterns applied to the system was to maximize stress on the high-speed buses. The tests were first validated on a known-good board. Then, faults were inserted and these same tests were run to verify that the faults could be found and diagnosed.
A number of different types of faults and tests were used in the experiment to simulate problems that might arise in a real world manufacturing environment.
The final results of the experimentation will be presented at ITC and provided to attendees at the conference.
For more information on ScanWorks for High-Speed Bus testing, click here.
For more information on ScanWorks for Intel IBIST,
click here.
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