DFT Analyzer™:
Following the Rules
Part of ASSET’s DFT Analyzer is based on a growing set of design-for-test rules which have been gleaned over the years from the experiences of ASSET’s application engineers as well as test engineers at user companies. Some rules reflect design practices that are fairly obvious, but others are more specific to boundary scan and they are probably rather obscure to most design engineers. For the typical design engineer who does not work with boundary scan on a daily basis, catching a mistake involving any of the specialized JTAG design practices will be more difficult to detect manually. As a result, the risk of a design mistake or oversight going undetected is high. The consequent effect of these undetected oversights is to drive up the cost of test significantly by reducing boundary scan’s test coverage.
One of the rules in DFT Analyzer, for example, questions whether the integrity of the JTAG signals on the board could be diminished by interference from other on-board signals. ASSET’s application engineers run into this situation quite often. A recent example, which occurred before DFT Analyzer was available, involved an ASSET application engineer in ASSET’s Boundary Scan Technology Center in China who discovered that the JTAG signals were overlaid on the same net that contained Serial Peripheral Interface (SPI) signals. The two sets of signals were interfering with each other, limiting design’s JTAG test coverage.
If DFT Analyzer had been available to the application engineer, it would have automatically and quickly detected the conflict and the application engineer could have gone home at a reasonable hour.
The DFT Analyzer database of rules is growing every day. New rules are being developed by ASSET’s application engineers and by many users as well.
If you haven’t already read about DFT Analyzer’s rapid return on investment, click here.
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