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There are plenty of good reasons for choosing boundary scan as a primary test technology. But, if it turns out that the JTAG coverage on a design is more limited than expected, there are usually just a few bad reasons to blame.

That’s where ASSET’s DFT Analyzer comes in.

The return-on-investment from DFT Analyzer is three-dimensional. First, it streamlines the testability analysis process, reducing significantly the time and effort that goes into each and every testability study. Second, the thorough nature of the analysis eliminates those bad reasons that should have been avoided in the first place. And the third pay-off comes from reducing opportunity costs that result when a product is late to market. Late products mean missed sales and that’s an opportunity cost.

Working the Numbers

A study based on data from a large electronics manufacturer showed that DFT Analyzer would reduce the company’s cost of producing each of its printed circuit board (PCB) designs by more than $5,000. And that’s just the first dimension of cost savings. The second dimension – avoiding the cost of more expensive alternative test methodologies, poorer quality products, increased board re-work and others – is an added benefit that will generate a pay-off over the life of the firm’s products.

Part of this particular OEM’s standard operating procedures is a testability analysis to determine the actual test coverage on every PCB design before it moves into production. Unfortunately, the test coverage designed into the circuit board and the actual test coverage when the design reaches production can diverge significantly. A testability analysis is performed to show where this divergence might come from while there’s still time to correct the problem.

The commitment to performing a testability analysis is not insignificant. In this case, the OEM estimated that it would take a design engineer two weeks and cost $7,200 in terms of sheer labor. That’s assuming the design engineer was fluent in all of the intricacies and nuances of JTAG DFT. Plus, any manually generated testability analysis is only as thorough as the powers of observation and concentration of the person performing the analysis. Poring over sometimes hundreds of pages of schematics is certainly a tiresome task. Lapses in concentration are to be expected and one missed interconnection, one misplaced signal or a single errant trace can severely limit the testability of a design once it reaches production.

In contrast to a manual testability study, a rules-based automated tool like DFT Analyzer streamlines the process by automatically examining a design and analyzing it against proven JTAG DFT practices. Oversights, mistakes and just plain errors can be avoided so that test costs remain low and product quality high. But the ROI pay-off on DFT Analyzer is more immediate than that.

Performing a thorough testability analysis on a complex board design with DFT Analyzer takes less than three days, as compared to the two weeks an engineer would need. At the same labor rate, that comes to a cost of only $2,160. The cost savings add up quickly, recouping the investment on the tool over a handful of board designs.

Here are the first-dimension cost savings from DFT Analyzer.

Testability Savings

By automating the testability analysis process, DFT Analyzer makes it accessible to manufacturers who might otherwise balk at the cost. Instead, a thorough testability analysis for each board design could become part of the company’s standard operating procedures. Over the long haul, that would increase overall test coverage on all designs, improving product quality and reducing ancillary costs such as re-work, repair and warranty returns.

Second-Dimension Savings

Beyond its ability to repeatedly perform cost-effective testability analyses, DFT Analyzer triggers a host of related cost savings that ensure a dramatic ROI on the tool itself. These include reducing the risk of lengthening a design’s development cycle to compensate for the loss of test coverage, reducing the number of PCBs that require rework, accelerating any required rework by pinpointing production defects and reducing the cost of in-circuit test (ICT) fixtures by decreasing the number of test points and the complexity of the fixtures.

Focusing on test point reduction alone can yield significant savings. For example, the same OEM cited earlier estimated a savings of $9,320 for each PCB. The firm projected that fewer test points would cut three days from board layout, reduce fixture cost by 20 percent and save three days from the time it normally took to generate non-boundary-scan tests. Here are the numbers:

Savings from Test Point Reductions

Millions in Savings!

Depending on the number of new boards produced each year, the savings can be quite substantial. Lucent recently performed an analysis that found it saved approximately one million dollars a year by taking advantage of these and other related savings. Reducing test points alone slashed the cost of Lucent’s ICT fixtures by close to $700,000 each year. The company saved another $21,000 from lower fixture maintenance costs.

In Lucent’s case, it examined the savings from a Fully Integrated ScanWorks for the 3070 ICT system. It figured that directly transferring boundary-scan tests from the design debug group to the 3070 cut test development time by 42 percent or $280,000 per year. All in all, the cost savings topped out close to a million dollars.

Lucent’s Million Dollar Savings

For a whitepaper on Lucent’s cost savings from the Fully Integrated ScanWorks for the 3070, click here.

Ensuring fast time-to-market

The third dimension of DFT Analyzer’s cost savings involves ensuring a product is delivered to the marketplace on time so that its market potential can be maximized. By minimizing many of the unexpected testability surprises that often derail new product introductions, DFT Analyzer is instrumental in reducing opportunity costs and ensuring a product hits its marketplace window.

Lost revenues caused by product delays have been estimated in the electronics industry by using the so-called ATEQ model. This formula projects lost revenue by taking into consideration the total expected revenue from a new product, how long the product’s introduction to the marketplace has been delayed and the expected window of opportunity for the product. The formula is as follows:

d = delay in the product’s introduction
w = the marketplace window or expected life of the product

Based on the ATEQ model, a one-day delay in introducing a product expected to generate $200 million over an 18-month life would cost the company $1 million in lost revenues. For each successive day of delay, the firm “pays” another $1,000,000 in opportunity costs.

DFT: The Key to Cost Savings

Of course, the ability to mine all of the costs savings possible from boundary scan begins back in board design. The surprise discovery of diminished boundary-scan test coverage reduces the amount of cost savings possible and, in addition, drives up the cost of test from its expected level. Re-designing a circuit board’s test strategy means delaying the production schedule and, more often than not, the new strategy will involve more expensive, more time-consuming test technologies than boundary scan. These unexpected cost increases will persist in each individual circuit board produced over the life of the product.