Connect - ASSET InterTech

For years the telecommunications industry has been coping with the dreaded “no-fault-found” (NFF) condition, a hidden nemesis that haunts equipment manufacturers and service providers alike. Fortunately, boundary scan can effectively reduce the magnitude of NFF as well as other concerns like remote management, provisioning and troubleshooting. As a result, you’re going to see JTAG test and in-system programming generating significant momentum in the telecom industry.

TEST DATA OUT

MicroTCA spec close to standardizing on boundary scan
by Adam Ley

Small- to mid-scale telecommunications and computing applications will have a new standard soon and it will include boundary-scan technology. The technical content of the MicroTCA (Telecommunications Computing Architecture) standard is virtually final. The specification has moved out of subcommittee and has been circulated to the general membership for review. Soon equipment manufacturers and system integrators in telecommunications and computing will have an easy and defined way to tap into the many benefits of boundary scan.

INSIDE ASSET

New ScanWorks helps reduce ICT test points,
cuts fixture costs
by Dave Bonnett

Eliminating test points from a printed circuit board (PCB) design has far reaching effects. Most notably, each removed test point reduces the cost and maintenance expense of the fixture needed to test the circuit board on an ICT system. Among several new capabilities, the new version of ScanWorks (3.8) has a Test Point Reduction Report which points out where test points in a design may be redundant because test coverage already is provided by boundary scan.

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BSDL files can validate a chip’s JTAG implementation

A process based on a device’s BSDL (Boundary Scan Description Language) file is the best way to validate that the chip’s JTAG features will work in the environment for which it was intended. That’s assuming the BSDL file is accurate. If it isn’t accurate – and there are plenty of opportunities for it to end up that way – then the BSDL file isn’t of much use to anyone. Fortunately, there are easy ways to ensure its accuracy.

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Boundary-Scan Technology Center opens in China

As a result of the growing technological and manufacturing importance of China, ASSET has opened a technology center in Shanghai. Staffed by Chinese nationals and managed by ASSET’s Fred Runco, director of Asian Business Development, the center provides direct technical support to companies in China. Plans for the future of the center include research and development at the site.

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Streamlining JTAG testability accelerates tool’s return-on- investment

Much like electronic design automation (EDA) tools which take the guesswork out of implementing sound board-level design practices, ASSET’s DFT Analyzer™, the JTAG world’s first design-for-test (DFT) tool, helps designers avoid oversights that add costs throughout a product’s life. By streamlining testability processes and, in some cases, providing them where they might be missing, the return-on-investment (ROI) on DFT Analyzer is tremendously quick.

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ASSET explains automated, rules-based JTAG DFT at European Board Test Workshop

Sometimes DFT (design-for-test) is like the weather. Everybody talks about it, but nobody does anything about it. Well, just as EDA tools automate design practices in general, ASSET has done something about automating the design process for boundary-scan test and in-system programming. At the European Board Test Workshop last month ASSET’s Adam Ley, chief technologist, and Kevin Fotheringham, an ASSET application engineer in the UK, highlighted how DFT Analyzer™, the industry’s first JTAG DFT tool, works.

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ASSET case study of high-speed bus testing presented at ITC

ASSET has created a technical paper on the structural testing of high-speed buses. The paper, which will be presented at the International Test Conference, Santa Clara, Calif., Oct. 24-26, takes a close look at Intel™ Interconnect Built In Self Test (IBIST), a test technology that Intel is embedding into its next-generation chipsets to lower the overall cost of test and more effectively validate high-speed buses. Embedded IBIST test structures can be accessed by boundary scan. The paper was written by Eric Johnson, a senior ASSET application engineer.

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Users awarded iPods for participating in survey

The recent user satisfaction survey brought ASSET a lot of good information. Some of this valuable feedback has already affected product plans and company strategies. In fact, one respondent said that since the survey was 20 questions long, we should give out two iPods instead of the one we offered. Well, he was right and so that’s what we did. A couple of lucky users were recently sent a new iPod Nano with a color display screen for participating in the survey.

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System-level JTAG shown in proof-of-concept demonstration

sjtag ASSET and Firecron Ltd of the UK recently teamed up to pull together a proof-of-concept demonstration of system-level boundary scan. The demo took place at the European Board Test Workshop, which attracted attendees from some of the largest electronics manufacturers in the world.

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