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New “Viewpoint” interview with ASSET CEO Glenn Woppman in Test and Measurement World:
“Relationships are key to ASSET’s success…”

New article by ASSET:
Embedded Systems Engineering: “Tackling Tough Problems”

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Agilent white paper on how ScanWorks has saved Lucent $1 million

News Release:
ASSET wins Best-in-Test for third year

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ASSET works to include system-level boundary-scan test into the MicroTCA spec

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ASSET hosts new online boundary-scan validation service

News Release:
DFT Analyzer™ validates design-for-test features before prototypes built


 

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INSIDE ASSET

Users Group gets sneak previews

Attendees at the recent ASSET Users Group were given a firsthand demonstration of the new DFT Analyzer, as well as briefings on the free online BSDL Validation Service, system-level JTAG, Internal JTAG (IJTAG), and new licensing options and help facilities in ScanWorks.

Technical Marketing Manager, Dave Bonnett, gave a presentation on the capabilities of DFT Analyzer while demonstrating how the industry’s first DFT tool for boundary scan can save manufacturers significantly by eliminating design re-spins. (For a story on DFT Analyzer from the previous issue of Connect, click here. Following Dave’s presentation, ScanWorks users offered their input on the product.

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Vice President of Sales and Marketing Alan Sguigna walked users through the free web-based BSDL Validation Service (www.asset-intertech.com/bsdl_service), a joint project of ASSET and Agilent Technologies that replaced an older, e-mail based service offered by Agilent. The new BSDL Validation Service, which checks the accuracy of BSDL files before any sample chips are produced, is hosted by ASSET and consists of two functional modules. The first module, the BSDL Syntax Checker, examines punctuation and spelling to determine whether the syntax of the BSDL file is accurate. Then it analyzes the BSDL file to locate any semantic discrepancies, such as missing instruction codes, register associations or register cells, as required by the standard. The service’s second module, Automatic Test Pattern Generation, creates a set of test vectors in a simple truth-table format. These vectors can effectively test a chip design during the simulation phase to verify that it meets many of the requirements of the IEEE 1149.1 boundary scan standard and that the BSDL accurately describes the silicon.

ASSET also offers a BSDL Silicon Validation service which complements the online BSDL service by validating the accuracy of a BSDL file against actual silicon after first devices are produced. A fixture is produced to validate each chip that is submitted. A nominal fee is required for the BSDL Silicon Validation Service.

Users also heard presentations on developments at either end of the boundary scan marketplace. For much of its history, boundary scan has been focused solidly on board-level test and in-system programming. Recent developments are expanding the scope of JTAG upward to multiple-board system-level testing and downward to the chip-level where boundary scan is being applied internally to test semiconductor devices.

Dave Bonnett again was called upon to explain the evolution of standardized System JTAG (SJTAG) methods. An ad hoc SJTAG group has met several times, including at ITC. The goal of the group, as Dave explained it, is “to define in a non-proprietary open standard the data contents and formats that are used to conduct communications between Test Manager platforms that are external to a system and the Embedded Test Controllers (ETCs) that are internal to the system, and between ETCs and the units under test (UUTs) they serve.” Simply stated, standardized techniques to do this would form the basis for SJTAG.

Users also heard a presentation from Ken Posse, a DFT consultant who has been chairman of an ad hoc study group looking into internal chip-level test issues such as timing relationships, logic analysis and others. Since ITC, this so-called Internal JTAG (IJTAG) effort has been sanctioned by the IEEE and is now known as IEEE P1687.

During his brief discussion, Posse indicated that the scope of the P1687 IJTAG effort is limited to access methodologies. “This standardization effort is intended to address how internal test and debug features are accessed, not the functioning of the features themselves,” Posse said. “The elements of standardized access include a description language for the characteristics of the features, a protocol language for communication with the features and interface methods to the features.” (For a more in-depth description of IJTAG in this issue of Connect, click here for an article by Posse.)

Arden Bjerkeli, ASSET’s director of customer applications support, told users about two innovative licensing options that were recently introduced, Self-Service Licensing and Emergency License Tokens. Self-Service Licensing significantly shortens the licensing process so a user can begin working with ScanWorks almost immediately. Now, after loading ScanWorks onto the target PC, Self-Service Licensing automatically launches and the user is asked to fill out a web-based form. When this is submitted, a new license is granted in a matter of minutes.

To help in peak load situations or in the event a PC running ScanWorks crashes, Emergency License Tokens are licenses that have a limited useful life. The tokens can be purchased online with a credit card and deployed when they are needed.

Also at the Users Group meeting, Manager of Online Communications, Darice Lang, explained the new HTML-based Help facilities in ScanWorks. Help documents are now provided as either Acrobat .pdf files or as HTML pages. Moreover, new indexing functionality and an online glossary of terms have enhanced the ease-of-use of ScanWorks.

The next ASSET Users Group meeting is scheduled for ITC 2007. Watch for future issues of Connect for more information.