 Lead-free deadline focuses attention on boundary scan and new ICT techniques
By Ben Bennetts
DFT Consultant
As a result of the European Union’s (EU) July 1 deadline for removing lead from all electronic systems, manufacturers who sell their products in Europe have had to devise new test strategies. And many of these strategies now include boundary scan. In addition, several papers presented at the International Test Conference (ITC) have shown how a test strategy including ICT and boundary scan can be adapted to lead-free assembly.
In a Connect article two years ago (Click here for that article.), I described some of the effects on test that the shift to lead-free solder would have. In particular, the article explained how the lead-free initiative, which the EU refers to as its Restriction of Hazardous Substances (RoHS) directive, will increase the importance of boundary scan test in many manufacturers’ test strategies.
 The different physical characteristics of lead-fee solder compounds have necessitated changes in manufacturing, assembly and test processes. For example, the reflow temperatures for lead-free solders can be significantly higher than it is for solders containing lead. Higher temperatures during manufacture necessitate higher-temperature components on boards and high-temperature devices have shorter shelf lives. Manufacturers are also concerned that higher flow solder temperatures could cause boards to warp, components to “tombstone” and tin whiskers to develop at solder joints.
Lead-free solders will also impact any test technology that requires physical contact with the printed circuit board, such as ICT, flying probe systems and manufacturing defect analyzers (MDA). Lead-free solders are more difficult for probes to penetrate than are solders containing lead. To properly test a lead-free solder joint or test point, a probe from an ICT system, for example, may have to exert greater pressure and this could create additional faults on the board.
Many electronic manufacturers are very concerned about the high level of stress any additional pressure from physical probes will place on a circuit board. This added stress flexes the board and this can have significant structural effects, such as broken traces or cracked joints. Typically, today’s ICT systems exert six ounces of pressure per probe on cleaned boards with solder compounds containing lead. With lead-free solder compounds, that pressure may increase to eight or 10 ounces, although manufacturers have resisted strenuously any increase beyond eight ounces. Even at eight ounces of pressure per nail, the effects can be significant. For example, a fixture with 5,000 nails exerting eight ounces of pressure each while simultaneously probing a circuit board would generate 2,500 pounds of pressure on the board. Assuming a man’s average weight is 192 pounds, that’s the equivalent of about 13 men standing on the circuit board. It’s easy to understand how this could cause cracked solder joints, “tombstoned” components and other faults.
The obvious reason why boundary scan is being included in manufacturers’ new test strategies is the fact that boundary scan puts no stress on circuit boards while it is testing solder joints and other structural aspects of the board. Moreover, because boundary scan and ICT test are often complementary, implementing additional boundary scan test coverage usually means that the number of ICT test points on a board as well as the number of probes in an ICT fixture can be significantly decreased. For each probe eliminated, less stress is exerted on the board during ICT test. In addition, fewer test probes means simpler, less costly ICT fixtures. And ICT maintenance costs are reduced because there are fewer probes to wear out and replace.
In addition to an added emphasis on boundary scan, the shift to lead-free solder compounds has spurred some new thinking and experimentation involving probing techniques and the composition of probes.
Recent ITC papers
In one paper from last year’s ITC in November in Austin , TX , Rosa D. Reinosa of Hewlett-Packard examined the repeatability of solid electrical contact from probes on an ICT fixture when lead-free solder compounds are used (“ Effect of Lead Free Solders on In-Circuit Test Process” P26.3). In her paper, Ms. Reinosa pointed out that the higher temperatures required by lead-free solders necessitate solder compounds with more flux by volume and more flux solids. The resulting flux residue could interfere with a probe as it makes contact and causes false fails. Even small increases in contact failures can have significant effects on the efficiency of a high-volume manufacturing line. More aggressive probe shapes and increasing the force exerted by the probes were also considered, although it was realized that increasing the pressure behind the probes would negatively affect the reliability of the circuit board. The paper concluded that the higher levels of flux contaminants in lead-free solders will decrease the useful life of probes.
In another ITC paper, Ken Parker of Agilent Technologies (“Bead Probes in Practice” P26.2) presented his findings from his experimentation with a new type of on-board test point and probe. He calls this technology “bead probes.” He introduced his work in this area at the 2004 ITC. A bead probe is a very small hemi-ellipsoid solder structure that typically lies on top of a signal trace . Bead probes are contacted with a flat-faced fixture probe. As the bead is contacted by the fixture probe, the head of the bead is flattened, displacing oxides and contaminants to provide good electrical contact. The force of the fixture probe in his experiments was only four ounces. |
