Connect - ASSET InterTech

Intel IBIST (Interconnect Built-In Self Test ) is a test architecture that Intel is integrating into its next-generation processor chips and chipsets to enable chip-to-chip interconnect testing and design validation of high-speed buses on a printed circuit board, so explained ASSET’s Tim Caffee at a briefing at the recent International Test Conference (ITC). Intel IBIST leverages the boundary-scan (IEEE 1149.1) specification as the hardware and software communication methodology for accessing and controlling embedded on-chip Intel IBIST capabilities.

Caffee said that Intel IBIST offers interconnect chip-to-chip test coverage for both DC defects and the newer high-speed AC-coupled buses like PCI Express. Intel IBIST is independent of bus protocols and is already being deployed by Intel to perform design validation and factory tests. The technology is also appropriate for end equipment manufacturers as it promises to shorten time-to-market for new products throughout the design and manufacturing phases.

The architecture for Intel IBIST features a test pattern generator that transmits test patterns across the bus where chip interconnects are being tested. A checker verifies whether the test patterns were transmitted correctly and error registers log any errors that are detected. Control registers establish the length and type of test that is transmitted.

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Intel IBIST is capable of both static, power-down testing as well as dynamic, at-speed testing. At-speed testing is particularly useful for high-speed AC-coupled buses where frequency faults can occur.

Intel IBIST supports several modes of operation that facilitate pre-boot debug, design validation and high-volume manufacturing test scenarios. In its so-called Push-Button Mode, Intel IBIST executes a pre-defined test suite. Examples of this mode might be a self-test in BIOS which is launched when the system powers up or a high-volume manufacturing test suite that is integrated with other processes on the assembly line.

Other modes of operation include a Fixed-Pattern Mode, which launches pre-defined worst-case tests or specific test patterns, and an Open-Pattern Mode, which is most often used during system bring-up and validation, and while manufacturing tests are being developed and debugged.

ScanWorks for Intel IBIST is available on a Development Station and on an Application Station. The ScanWorks Intel IBIST Development Station is appropriate to users who want to develop custom tests that use Intel IBIST’s facilities to test high-speed buses. The ScanWorks Intel IBIST Application Station is being adopted by users who require a simple, turnkey solution for testing high speed serial buses, such as PCI Express, on a specific platform. For Application Stations, ASSET sets up the tests so little or no training is required.

For more information on ScanWorks for Intel IBIST, click here.