 Internal JTAG – Where it originated and where it’s going
By Ken Posse
Chairman, IEEE P1687 Working Group
Semiconductor technology is rapidly outpacing our ability to test, diagnose and characterize device designs. Truthfully, it seems that this has always been the case, but in many ways it is becoming even more critical today. Semiconductor devices, such as SoCs (system-on-a-chip), are often designed with such a multiplicity of functions involving logic that is very complex and deep that it is imperative (for the sake of quality) that engineers have the ability to manipulate and control small sections of the circuitry in order to properly test and characterize a device.
For example, memories buried deep within a device can frequently be adequately tested only through the use of Built In Self Test (BIST). SERDES (serializer/deserializer or high-speed serial I/O) cannot be adequately characterized without the ability to “see” the received signals exactly as the chip sees them. Timing margins, power margins, signal quality and other aspects within an ASIC clearly cannot be measured without the ability to manipulate and observe circuitry inside a semiconductor device.
Additionally, the validation of circuit design often requires the coordination of information flowing between devices. For example, bit error rate characterization requires that a test originate from one device and terminate at another and that the two (or more) devices are synchronized. Measuring of the effects of other externally-occurring signals often requires some sort of synchronization or triggering as well.
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The good news in all of this is that the mechanisms for making most, if not all, of these measurements and controlling the logic within a chip already exists. BIST engine controls, SERDES I/O timing and receive level manipulation (as well as driver pre-emphasis), bit error rate test (BERT) characterization and other measurements are all within the capability of today’s designs and in fact are all in use in ASICs being designed today. The bad news is that there are no standard control mechanisms and protocols in place to address these mechanisms. As a result, designers have created a plethora of access methods and data protocols including multiplexed I/O pins, specialized serial I/O, the use of Internal Scan (ISCAN) and others. Because of the multiplicity of access methods, and the lack of any mechanism for describing the access protocols, the use and transportability of tests using these features can be extremely complicated.
IJTAG Beginnings
This sea of complexity is what prompted the initial investigation into some sort of access and control standardization for this type of capability. This effort began as an open meeting two years ago at the International Test Conference. The meeting, chaired by Jeff Rearick of Agilent Technologies, stimulated enough interest to warrant pursuing it further. As a result, the IEEE P1687 -- Draft Standard for Access and Control of Instrumentation Embedded Within a Semiconductor Device working group was formed. This team, often referred to as IJTAG (Internal JTAG) has been at work for about nine months now. The group’s purpose is to look at the test and access mechanisms in use today and to produce a standard based on the IEEE 1149.1 Test Access Port (TAP) controller that will allow users to access and control these internal circuits. (Within the P1687 Working Group, these circuits are collectively referred to as “instruments”.) Additionally, the team is working toward a standard mechanism for describing both the architecture of an “instrument” (for example, a BIST engine or a SERDES I/O filter) so that the access protocols can be automatically determined by test equipment. The most likely candidates for this protocol description language are either BSDL or CTL, or possibly both.
When completed, the extensions to the chosen language(s) would allow test generation software to automatically produce the command sequences and vector data to control embedded instruments.
Where It Will Lead
Once completed and adopted, the standard would allow external test and characterization equipment to connect to an IEEE 1149.1 port, to read an architectural description file and a test procedural description file, and based on these files to make adjustments interactively to the circuitry. For example, the operation might change the phase of a SERDES receive strobe or change the frequency of a phase lock loop routine (PLL). Alternatively, the operation could trigger and capture measurements on that circuitry, such as timing analysis of critical paths or power-consumption analysis during periods of very active logic transitions. In addition, the capabilities I am describing could also extend to executing embedded test circuitry such as memory and logic BIST, and collecting and analyzing the results.
Since the structural and behavioral models of the instrumented semiconductor devices provide the necessary information to characterization and/or test equipment, it will no longer require complex programming efforts on the part of the test engineer.
For more information on this subject, or if there are questions regarding the standard, please feel free to contact the author by email at: kepos@comcast.net.
About the author --
Ken Posse is a Semiconductor DFT consultant and chairman of the IEEE P1687 (IJTAG) Working Group. Ken holds a Bachelors Degree in Aerospace Engineering and a Masters Degree in Computer Engineering. He was formerly a Systems Architect and Project Manager at Agilent Technologies and Chief Technical Officer of Teseda Corp. Ken currently lives in Fort Collins , Colorado and can be reached at kepos@comcast.net.
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