Connect - ASSET InterTech

For the third year in a row, ASSET and our products have been recognized by Test & Measurement World magazine with a Best In Test award. As the only company to be recognized year, after year, after year for innovative software solutions, the 2006 Best In Test honorable mention we won for DFT Analyzer is a testament to our ability to develop collaborative and mutually beneficial relationships with our customers, which, in turn, drive our technology roadmaps.

TEST DATA OUT

Accuracy of BSDL has far-reaching consequences
by Dave Bonnett

Many chip designers may think that generating an accurate BSDL (Boundary Scan Description Language) file for a chip is fairly straightforward. Just design the chip and let the EDA system spit out the BSDL file. Unfortunately, it’s not quite as easy as that. Moreover, the consequences of an inaccurate BSDL file can be quite costly, stretching far beyond the foundry. Now there are a couple of solutions.

INSIDE ASSET

ASSET recognized as Best-in-Test for third consecutive year!

This year’s Best In Test awards from Test and Measurement World magazine represents a couple of firsts: one for the boundary scan industry and another for ASSET. ASSET’s honorable mention for its DFT Analyzer is the first time any boundary scan company has ever won three straight Best In Test honors and the first time ASSET has won three years in a row.

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Flexible configurations accelerate integration of ScanWorks with ICT systems

Elegantly simple, yet profoundly flexible, integrating ScanWorks and its powerful boundary-scan tools with practically any brand name In-Circuit Test (ICT) system has gained significant momentum among electronic manufacturers. It’s fast, it’s easy and combining ICT with boundary scan improves test coverage.

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Getting the lead out puts boundary scan in the mix
By Ben Bennetts

With the approach of the July 1, 2006 deadline for lead-free electronics in Europe, manufacturers are considering alternatives to their traditional test strategies. In many cases, the emerging strategies include boundary scan. Ben Bennetts, a prominent DFT consultant, takes a look at the situation and recommends several papers that were presented at the recent International Test Conference.

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IJTAG effort strives to simplify chip-level test
by Ken Posse

Ken Posse, chairman of the IEEE P1687 Internal JTAG (IJTAG) working group, reports on the progress the group has made as it standardizes the testing and characterizing of circuits on semiconductor devices. The IJTAG standard will be based on the IEEE 1149.1 Boundary Scan Test Access Port (TAP) controller which will provide the access needed to control internal chip circuits.

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ITC attendees briefed on ScanWorks for Intel® IBIST
by Tim Caffee

At the recent International Test Conference (ITC), Tim Caffee, ASSET’s Vice President of Design Validation, gave a briefing on ScanWorks for Intel IBIST (Interconnect Built-In Self Test), Intel’s new embedded test technology. The on-chip Intel IBIST facilities are accessed through boundary scan. ASSET is the only commercial JTAG system to support Intel IBIST at this time.

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User Group gets the inside skinny on new products, services and support

Attendees at the recent ASSET Users Group meeting at the International Test Conference (ITC) got a glimpse of an exciting new product called DFT Analyzer, as well as the recently unveiled free online BSDL Validation Service. Other interesting presentations described recent developments in system-level JTAG and Internal JTAG (IJTAG), as well as improvements to ScanWorks’ online help facilities.

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ASSET grades highly with users

Initial results from a satisfaction survey show that the ASSET user community is quite impressed with the company’s technical support capabilities. More than 90 percent of those who responded to the survey gave the support department a good or excellent grade.

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