Connect - ASSET InterTech

ASSET’s new DFT Analyzer reduces manufacturing and tests costs by verifying the design-for-test (DFT) features in a circuit board design before any prototypes are assembled. In addition, DFT Analyzer determines the extent of a design’s boundary-scan test coverage and recommends changes that would increase coverage. The new product can be implemented separately from ScanWorks, although the boundary-scan description which is output from DFT Analyzer can be imported directly into ScanWorks, where a set of boundary-scan tests can be generated with minimal effort. In addition, existing ScanWorks projects can be imported into DFT Analyzer to determine where and how test coverage could be improved.

DFT Analyzer is made up of three tools which are employed at different stages in product development. First, as schematics are being developed, DFT Analyzer’s automated Checklist queries a designer or test engineer about the testability features included in a design. These questions are based on sound DFT principles derived by ASSET from its many years of working with board designers to optimize boundary-scan test coverage. In addition, design practices specific to the organization can be included in the Checklist to ensure consistency across all of a company’s designs.

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Next, DFT Analyzer’s Design Verification tool can be launched after computer aided design (CAD) information has been compiled. With the CAD data that is imported into DFT Analyzer, the Design Verification tool determines whether any pre-established DFT rules have been broken or overlooked. The tool recommends solutions if it encounters a broken rule. In addition, company-specific DFT rules can be added to those already included in DFT Analyzer.

DFT Analyzer’s third tool, Test Coverage Analysis, is engaged during the final stages of design before first prototypes of the board are manufactured. This tool determines the extent of boundary-scan test coverage when certain types of tests, such as interconnect, memory and others, are run on the circuit board. In addition, the report contains information concerning which ICT test points can be eliminated by substituting a boundary-scan test for the ICT process. Eliminating ICT test points saves board space and reduces the complexity and cost of ICT test fixtures. In addition, the Test Coverage Analysis module can output results to the DFT Analyzer’s design browser which graphically displays the available test coverage in a schematic view. This graphical representation of the design can be quite useful during design reviews and throughout the product’s entire lifecycle.

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The final output of DFT Analyzer is a complete boundary-scan description of the design that can be imported directly into the ScanWorks test-generation engine. A comprehensive suite of boundary-scan tests can then be generated and optimized for the first prototype boards. Subsequently, this JTAG test suite can be re-used through the manufacturing process as well as system test and field support.

DFT Analyzer at a Glance

DFT Analyzer runs independently of ScanWorks
Intuitive interface eases deployment
Output displayed in graphical design browser for design reviews and other purposes
Fully supported by ASSET
Runs on a typical PC with no extra hardware
Available as single-user or networked application
Composed of three tools: Checklist, Design Verification and Test Coverage Analysis
Checklist ensures testability consistency across the entire organization. Company-specific rules are easily added.
Design Verification verifies that the design has implemented the organization’s predefined DFT rules. It is based on same design data as ScanWorks projects. Output can be imported by ScanWorks as the basis for automatic test generation. Reports where DFT rules have not been followed and recommends corrective action. Output can be displayed graphically in DFT Analyzer’s design browser. Company-specific rules which access and analyze design data can be easily added to the database.
Test Coverage Analysis determines the amount of boundary-scan test coverage available on the design. Reports on where test points can be eliminated. Outputs report in CSV format for easy migration to ICT systems. Draws on ScanWorks test pattern generation algorithms to ensure accurate reports.