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INSIDE ASSET

An evolving 1149.1 standard

Much has changed in the 16 years since the official approval of the IEEE 1149.1 Boundary Scan Standard. If the events leading up to and taking place at the IEEE Test Week and its International Test Conference (ITC) are any indication, the venerable boundary scan standard may soon reach out in several directions.

Internal JTAG (IJTAG) and System JTAG (SJTAG) are currently ad hoc groups that are exploring device-level (IJTAG) and system-level (SJTAG) modifications and additions to the original 1149.1 standard. Both internal- and system-level JTAG issues will be discussed at several upcoming events, including the Board Test Workshop the week before ITC (Nov. 3-4 in Fort Collins, Col.) and at ITC itself (Nov. 6-11 in Austin, Tex.).

The IJTAG group is examining how the boundary scan Test Access Port (TAP) might be used for access to a variety of test-and-measure instruments embedded on-chip. These instruments would support device characterization, and structural and functional test at the level of the device itself. The elements of IJTAG access might include a description language for characteristics of the embedded instruments, a protocol language for communicating with the instruments and a method for interfacing to the on-chip instruments.

The IJTAG initiative actually got under way at the 2004 ITC. The group has defined its scope and purpose, and a technical paper will be presented on IJTAG at ITC 2005. The group, which is chaired by Ken Posse, a consultant to ASSET, will meet on Thursday, Nov. 10, at ITC. A status paper on IJTAG will be presented at the Board Test Workshop the week before ITC. (For a list of upcoming boundary scan activities leading up to and including ITC, click here.)

The second boundary-scan group, the SJTAG group, has grown out of a need recognized by suppliers to the telecommunications industry. In recent years, many telecom companies have adopted a system-level approach to testing and troubleshooting. Many of these implementations are based on JTAG as a backplane test bus for accessing tests embedded on-board or for downloading tests that are applied as part of a field service application. Several telecom equipment suppliers such as Lucent, Ericsson, Cisco and Motorola have already deployed to some degree system-level test with boundary scan, but now a higher degree of sophistication is being sought and that will require a standardization effort.

In its initial discussions, the SJTAG group has identified the need for a language or communications protocol for command control and for test data delivery and response. This language should be independent of any vendor as well as any particular test bus implementation. The test manager in such a system-test deployment could be local or remote.

The SJTAG group, which is headed up by Ben Bennetts, also a consultant to ASSET, first met in May of 2005. Since then, the group has been working on a white paper describing the issues it is addressing and several potential solutions. This white paper will be presented at the Board Test Workshop the week before ITC. The SJTAG group has scheduled an open meeting for Thursday of ITC.

See below for a list of IJTAG and SJTAG activities at the Board Test Workshop and ITC.

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Event Activity Speaker

Board Test Workshop, November 3 – 4, 2005 , Fort Collins , CO .

“SJTAG white paper”

 

 

“The solution for your system JTAG language”

 

“IJTAG status”

SJTAG core group, Gunnar Carlsson (Ericsson) lead author

 

Mike Westermeier, ASSET InterTech

 

IJTAG core group, Jeff Rearick (Agilent) lead author

ITC, November 6 – 11, Austin , TX

November 7

 

 

 

 

November 9

 

 

 

 

 

 

 

November 10

 

 

TUTORIAL 15 (NEW)
Designing Testable Multi-board Systems Using 1149.1Architectures

 

Session 32
4 papers on system-level applications of boundary scan

 

 

 

 

 

IJTAG Open Meeting

 

 

 

Presenters Ben Bennetts (Bennetts Associates) and Mike Westermeier (ASSET InterTech)

 

Includes SJTAG-related papers from Brad van Treuren (Lucent) and Gunnar Carlsson (Ericsson) plus the IJTAG initiative (IJTAG core group, Jeff Rearick lead author)

 

Contact Ken Posse, IJTAG Chairman, at kepos@comcast.net for more details.

Contact Ben Bennetts, SJTAG Chairman, at ben@dft.co.uk for more details.

Electronics System Test Workshop,November 11, Austin , TX

“System Test in Advanced TCA® and µTCA” (proposed)

 

“Objectives and status of the System JTAG (SJTAG) initiative” (proposed)

Dave Bonnett, ASSET InterTech

 

 

Ben Bennetts, Bennetts Associates