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INSIDE ASSET |
New ScanWorks Version 3.6 now available
Chief among the new capabilities and functionality included in ScanWorks 3.6 are enhancements to 1149.6 AC testing to enable merged actions that test both AC interconnects and 1149.1 DC interconnects, as well as a new graphical fault display feature which automatically illustrates the fault coverage provided by a test suite at the net, device and pin levels.
The enhanced IEEE 1149.6 High-Speed Bus testing capabilities in ScanWorks make it the only JTAG test system with an automated and complete solution for 1149.6 testing. The new capabilities shorten test application times and simplify the test flow by combining tests for AC and DC interconnects in the same test action. These enhancements were developed in concert with early adopters of the IEEE 1149.6 standard for high-speed bus testing. (For more information on ScanWorks’ 1149.6 tools, click here.) If the test clock (TCK) frequency and delay times are compatible for all pins on a chain, distinct tests for DC-interconnects and AC-interconnects can be merged automatically by ScanWorks, creating a single action to test all combinations of pins in one seamless process. The screen below shows just how easy it is to generate combined 1149.1 and 1149.6 test actions. |
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Graphical Fault Coverage
The graphical nature of ScanWorks’ Interconnect Coverage Report illustrates the test coverage level of a design instantaneously, eliminating any tedious manual analysis of coverage data. Test developers know immediately the coverage level they have achieved and precisely where additional test development will yield improved coverage.
The Interconnect Coverage Report has links to a schematic or layout view in the ScanWorks Design Browser where all of the circuit board’s nets in a specific coverage class are highlighted graphically. In addition, the ScanWorks Combined Coverage Report comes with links to a graphical fault mapping view that shows the opens coverage on all pins, the shorts coverage on all nets and the overall coverage on all devices at the pin level.
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The Interconnect Fault Coverage Report (above) shows graphically which device pins have test coverage. A white dot on a pin indicates test coverage. Click to enlarge.
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Embedded System-Level Boundary Scan
ScanWorks has been enhanced with automatic test vector conversion capabilities that are particularly useful in embedded system-level JTAG applications. Because the size of test vectors is a critical factor in embedded applications, ScanWorks can automatically convert serial vector format (SVF) files, a standard boundary scan vector format, to any of several more compact binary formats such as ASSET’s serial binary stimulus format (SBSF) and other formats supported by the suppliers of embedded boundary-scan controller devices, including Alliance Semiconductor, Firecron Ltd, National Semiconductor, Texas Instruments and others.
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New Licensing Options
Several innovative licensing options give ASSET users the assurance that they will always have access to ScanWorks even in emergencies, such as the crash of a personal computer. Self-service licensing activates ScanWorks in a matter of seconds while emergency license tokens keep ScanWorks up and running in emergencies or at times of peak work load. (For a complete description of the new licensing options in this issue of Connect, click here.)
Improving User Productivity
Several ScanWorks features have been enhanced to make certain functions easier to use and to improve the productivity of users. One such enhancement involves I2C programming. Now, ScanWorks users can specify multiple source files for I2C programming operations so that a single I2C programming operation can load multiple locations on a printed circuit board with different data. At run time, test operators can enter data to be loaded into memory by manually typing in the data or by way of a barcode scanner.
In addition, the flow of ScanWorks test sequences has been improved so that the results of one step in a sequence will not derail the entire sequence. For example, a ScanWorks test engineer might decide to invert the action taken as the result of a certain step in a sequence. Instead of following the sequence flow defined as the “PASS” outcome for a certain step, the engineer might want a pass outcome to follow the “FAIL” sequence of steps. Another example would be when the engineer would prefer that the results of a sequence indicate a PASS condition even when a step in the sequence had failed. This outcome is useful in several instances. For example, it can be used to verify and update, if needed, the version of the contents of a flash memory device. The code version number is read from the flash device and compared with the expected value. If the version numbers are not the same, the step fails, but the ScanWorks action could go on to update the device with the correct version. Although the compare failed, the action is successful because the correct version of code is now stored in the flash memory.
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